/**
 @file sys_usw_port.c

 @author  Copyright (C) 2011 Centec Networks Inc.  All rights reserved.

 @date 2011-11-22

 @version v2.0

*/

/****************************************************************************
 *
* Header Files
*
****************************************************************************/
#include "sal.h"
#include "ctc_error.h"
#include "ctc_debug.h"
#include "ctc_dot1ae.h"
#include "ctc_interrupt.h"
#include "ctc_warmboot.h"
#include "ctc_stacking.h"

#include "sys_usw_common.h"
#include "sys_usw_port.h"
#include "sys_usw_chip.h"
#include "sys_usw_scl_api.h"
#include "sys_usw_internal_port.h"
#include "sys_usw_chip.h"
#include "sys_usw_ftm.h"
#include "sys_usw_register.h"
#include "sys_usw_dmps.h"
#include "sys_usw_mac.h"
#include "sys_usw_peri.h"
#include "sys_usw_wb_common.h"

#include "drv_api.h"

/****************************************************************************
 *
* Defines and Macros
*
*****************************************************************************/

#define SYS_MAX_FRAME_VALUE (16 * 1024)

#define SYS_SGMAC_RESET_INT_STEP   (ResetIntRelated_ResetSgmac1_f - ResetIntRelated_ResetSgmac0_f)

#define SYS_SGMAC_EN_PCS_CLK_STEP  (ModuleGatedClkCtl_EnClkSupSgmac1Pcs_f - ModuleGatedClkCtl_EnClkSupSgmac0Pcs_f)

#define SYS_SGMAC_XGMAC_PCS_CLK_STEP  (ModuleGatedClkCtl_EnClkSupSgmac5XgmacPcs_f - ModuleGatedClkCtl_EnClkSupSgmac4XgmacPcs_f)

#define SYS_GMAC_RESET_INT_STEP  (ResetIntRelated_ResetQuadMac1Reg_f - ResetIntRelated_ResetQuadMac0Reg_f)

#define GMAC_FLOW_CTL_REG_ID_INTERVAL 20
#define SGMAC_FLOW_CTL_REG_ID_INTERVAL 42
#define XGMAC_FLOW_CTL_REG_ID_INTERVAL 36

#define SYS_PORT_SOURCE_PORT     1
#define SYS_PORT_HIGH_PRIO_PORT  2
#define SYS_PORT_LOW_PRIO_PORT   0

#define SYS_PORT_SOURCE_CHAN     0
#define SYS_PORT_LOW_PRIO_CHAN   1
#define SYS_PORT_HIGH_PRIO_CHAN  2

#define SYS_PORT_BPE_MAX_ECID   4095
#define SYS_PORT_BPE_MAX_NAME_SPACE   2047

#define SYS_PORT_MAX_ESID   0xFF

#define SYS_MLAG_ISOLATION_RESERVE_PORT_MASK 0xffffff00

#define SYS_LINKAGG_MC_MAP_PBM_PORTID(lport, port_type, port_id)\
    do{\
      port_type = (lport >> 7)&0x1;\
      port_id   = (lport & 0x7F);\
    }while(0)

enum sys_port_egress_restriction_type_e
{
    SYS_PORT_RESTRICTION_NONE = 0,                    /**< restriction disable */
    SYS_PORT_RESTRICTION_PVLAN = 1,                   /**< private vlan enable */
    SYS_PORT_RESTRICTION_BLOCKING = 2,                /**< port blocking enable */
    SYS_PORT_RESTRICTION_ISOLATION = 4                /**< port isolation enable */
};
typedef enum sys_port_egress_restriction_type_e sys_port_egress_restriction_type_t;


enum sys_scl_key_mapping_type_e
{
    SYS_PORT_KEY_MAPPING_TYPE_DRV2CTC,
    SYS_PORT_KEY_MAPPING_TYPE_CTC2DRV,
    SYS_PORT_KEY_MAPPING_TYPE_NUM
};
typedef enum sys_scl_key_mapping_type_e sys_scl_key_mapping_type_t;

enum sys_port_preamble_type_e
{
    SYS_PORT_PREAMBLE_TYPE_8BYTE,
    SYS_PORT_PREAMBLE_TYPE_4BYTE,
    SYS_PORT_PREAMBLE_TYPE_NUM
};
typedef enum sys_port_preamble_type_e sys_port_preamble_type_t;

struct sys_scl_type_map_s
{
    uint8 hash_en;
    uint8 use_macda;
    uint8 vlan_high_priority;
    uint8 drv_type;
    uint8 ctc_type;
};
typedef struct sys_scl_type_map_s sys_scl_type_map_t;

typedef struct
{
    uint32 hash_type;
    uint32 tcam_type;
    uint32 tcam_en;
    uint32 vlan_high_priority;
    uint8  use_label;
    uint8  label;
    uint8  is_userid;
    uint8  use_macda;
    uint8  ipv4_tunnel_en;
    uint8  ipv4_gre_tunnel_en;
    uint8  rpf_check_en;
    uint8  auto_tunnel;
    uint8  nvgre_en;
    uint8  v6_nvgre_en;
    uint8  v4_vxlan_en;
    uint8  v6_vxlan_en;
} sys_usw_igs_port_scl_map_t;

typedef struct
{
    uint32 hash_type;
    uint8  use_label;
    uint8  label;
} sys_usw_egs_port_scl_map_t;


/****************************************************************************
 *
* Global and Declaration
*
*****************************************************************************/
sys_port_master_t* p_usw_port_master[CTC_MAX_LOCAL_CHIP_NUM_PP] = {NULL};

#define TCAML2KEY       0
#define TCAML3KEY       1
#define TCAML2L3KEY     2
#define TCAMUSERIDKEY   3
#define TCAMUDFSHORTKEY 4
#define TCAMUDFLONGKEY  5
#define TCAMUDFQUADKEY  6
#define TCAMPKTDATAKEY  7
#define TCAMDISABLE     8

/*MCHIP_CAP(SYS_CAP_SCL_LABEL_FOR_VLAN_CLASS) MCHIP_CAP(SYS_CAP_SCL_LABEL_FOR_IPSG)*/
extern int32
sys_usw_ip_source_guard_set_default_entry(uint8 lchip, uint16 lport, uint32 gport, uint32 agg_port_cnt, uint16 tid);
extern int32
sys_usw_ip_source_guard_remove_default_entry(uint8 lchip, uint32 gport, uint8 scl_id);
extern int32
sys_usw_ip_source_guard_add_default_entry(uint8 lchip, uint32 gport, uint8 scl_id);
extern uint8
sys_usw_acl_get_league_block(uint8 lchip, uint8 block_id, uint8 * block_list);
extern int32
sys_usw_mac_set_capability(uint8 lchip, uint32 gport, ctc_port_capability_type_t type, uint32 value);
extern int32
sys_usw_vlan_class_set_default_action(uint8 lchip, uint16 lport, uint8 scl_id, uint8 is_add);
STATIC int32
_sys_usw_port_set_wlan_port_type(uint8 lchip, uint32 gport, uint32 value);
STATIC int32
_sys_usw_port_set_wlan_port_route(uint8 lchip, uint32 gport, uint32 value);
extern int32
sys_usw_mac_wb_sync(uint8 lchip,uint32 app_id);
extern int32
sys_usw_internal_port_wb_sync(uint8 lchip,uint32 app_id);
extern int32
_sys_usw_internal_port_allocate(uint8 lchip, ctc_internal_port_assign_para_t* port_assign, sys_nh_info_dsnh_t* p_dsnh_info);
extern int32
_sys_usw_internal_port_release(uint8 lchip, ctc_internal_port_assign_para_t* port_assign);
extern int32
sys_usw_inband_get_port_index(uint8 lchip, uint32 gport, uint8* p_index);

extern int32
sys_usw_dmps_set_direction_property(uint8 lchip, uint32 gport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32 value);
extern int32
sys_usw_dmps_get_direction_property(uint8 lchip, uint32 gport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32* p_value);

/****************************************************************************
 *
* Function
*
*****************************************************************************/
int32
_sys_usw_port_add_tx_max_frame_size(uint8 lchip, uint16 frame_size, uint16 old_frame_size, uint8* frame_idx)
{
    uint32 cmd = 0;
    uint32 value = 0;
    uint8 is_find = 0;
    uint8 is_fst_unused = 0;
    uint8 fst_unused_idx = 0;
    uint8 index = 0;

    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_MASTER, 1);
    for (index=0; index<SYS_PORT_TX_MAX_FRAME_SIZE_NUM; index++)
    {
        if (0 != p_usw_port_master[lchip]->tx_frame_ref_cnt[index])
        {
            cmd = DRV_IOR(NetTxMaxLenCfg_t, NetTxMaxLenCfg_maxCheckLen_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
            if (old_frame_size && (old_frame_size == value))
            {
                p_usw_port_master[lchip]->tx_frame_ref_cnt[index]--;
                if (0 == p_usw_port_master[lchip]->tx_frame_ref_cnt[index])
                {
                    fst_unused_idx = index;
                    is_fst_unused = 1;
                }
            }

            if (frame_size == value)
            {
                *frame_idx = index;
                is_find = 1;
                p_usw_port_master[lchip]->tx_frame_ref_cnt[index]++;
            }
        }
        else if (0 == is_fst_unused)
        {
            fst_unused_idx = index;
            is_fst_unused = 1;
        }
    }

    if ((0 == is_find) && (0 == is_fst_unused))
    {
        return CTC_E_NO_RESOURCE;
    }
    else if ((0 == is_find) && (1 == is_fst_unused))
    {
        *frame_idx = fst_unused_idx;
        value = frame_size;
        cmd = DRV_IOW(NetTxMaxLenCfg_t, NetTxMaxLenCfg_maxCheckLen_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, fst_unused_idx, cmd, &value));
        p_usw_port_master[lchip]->tx_frame_ref_cnt[fst_unused_idx]++;
    }

    return CTC_E_NONE;
}
#if 1
STATIC int32
_sys_usw_port_tx_max_frame_size_init(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 tx_max_chk_en[2] = {0};
    uint8 frame_idx = 0;
    uint32 index = 0;
    uint32 value = 0;

    if (DRV_FROM_TMM(lchip))
    {
        NetTxMaxMinLenCfg_m nettx_len_cfg;
        sal_memset(&nettx_len_cfg, 0, sizeof(NetTxMaxMinLenCfg_m));

        SetNetTxMaxMinLenCfg(V, cfgMaxPktLen_f, &nettx_len_cfg, MCHIP_CAP(SYS_CAP_PORT_MAX_FRAMESIZE_MAX_VALUE));
        cmd = DRV_IOW(NetTxMaxMinLenCfg_t, DRV_ENTRY_FLAG);
        for (index = 0; index < DRV_TABLE_MAX_INDEX(lchip, NetTxMaxMinLenCfg_t); index++)
        {
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &nettx_len_cfg));
        }

        value = 1;
        cmd = DRV_IOW(NetTxMiscCtl_t, NetTxMiscCtl_cfgMaxLenChkEn_f);
        for (index = 0; index < DRV_TABLE_MAX_INDEX(lchip, NetTxMiscCtl_t); index++)
        {
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
    }
    else
    {
        sal_memset(tx_max_chk_en, 0xFF, sizeof(tx_max_chk_en));
        cmd = DRV_IOW(NetTxMaxLenChkEn_t, NetTxMaxLenChkEn_maxLenChkEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &tx_max_chk_en));
        CTC_ERROR_RETURN(_sys_usw_port_add_tx_max_frame_size(lchip, MCHIP_CAP(SYS_CAP_PORT_MAX_FRAMESIZE_MAX_VALUE), 0, &frame_idx));
        value = frame_idx;
        for (index = 0; index < MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM); index++)
        {
            cmd = DRV_IOW(NetTxMaxMinLenPortMap_t, NetTxMaxMinLenPortMap_maxLenPortSel_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
        p_usw_port_master[lchip]->tx_frame_ref_cnt[value] += (MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM) - 1);
    }
    return CTC_E_NONE;
}
#endif

STATIC int32 _sys_usw_port_set_sd_action(uint8 lchip, ctc_direction_t dir, uint32 index, uint32 act_type)
{
    uint32 cmd = 0;
    uint32 value = 0;

    if (DRV_IS_DUET2(lchip))
    {
        switch(act_type)
        {
            case CTC_PORT_SD_ACTION_TYPE_NONE:
                value = 0;
                break;
            case CTC_PORT_SD_ACTION_TYPE_DISCARD_OAM:
                value = 5;
                break;
            case CTC_PORT_SD_ACTION_TYPE_DISCARD_DATA:
                value = 6;
                break;
            case CTC_PORT_SD_ACTION_TYPE_DISCARD_BOTH:
                value = 7;
                break;
            default :
                return CTC_E_INVALID_PARAM;
        }
        if ((CTC_INGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
        {
            cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_pbbPortType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
        if ((CTC_EGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
        {
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_pbbPortType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
    }
    else
    {
        switch(act_type)
        {
            case CTC_PORT_SD_ACTION_TYPE_NONE:
                value = 0;
                break;
            case CTC_PORT_SD_ACTION_TYPE_DISCARD_OAM:
                value = 1;
                break;
            case CTC_PORT_SD_ACTION_TYPE_DISCARD_DATA:
                value = 2;
                break;
            case CTC_PORT_SD_ACTION_TYPE_DISCARD_BOTH:
                value = 3;
                break;
            default :
                return CTC_E_INVALID_PARAM;
        }
        if ((CTC_INGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
        {
            cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_sdChkType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
        if ((CTC_EGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
        {
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_sdChkType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
    }
    return CTC_E_NONE;
}

STATIC int32 _sys_usw_port_get_sd_action(uint8 lchip, ctc_direction_t dir, uint32 index, uint32* act_type)
{
    uint32 cmd = 0;
    uint32 value = 0;
    if (DRV_IS_DUET2(lchip))
    {
        if (CTC_INGRESS == dir)
        {
            cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_pbbPortType_f);
        }
        else if (CTC_EGRESS == dir)
        {
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_pbbPortType_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        switch(value)
        {
            case 5:
                *act_type = CTC_PORT_SD_ACTION_TYPE_DISCARD_OAM;
                break;
            case 6:
                *act_type = CTC_PORT_SD_ACTION_TYPE_DISCARD_DATA;
                break;
            case 7:
                *act_type = CTC_PORT_SD_ACTION_TYPE_DISCARD_BOTH;
                break;
            default :
                *act_type = CTC_PORT_SD_ACTION_TYPE_NONE;
                break;
        }
    }
    else
    {
        if (CTC_INGRESS == dir)
        {
            cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_sdChkType_f);
        }
        else if (CTC_EGRESS == dir)
        {
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_sdChkType_f);
        }
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        switch(value)
        {
            case 1:
                *act_type = CTC_PORT_SD_ACTION_TYPE_DISCARD_OAM;
                break;
            case 2:
                *act_type = CTC_PORT_SD_ACTION_TYPE_DISCARD_DATA;
                break;
            case 3:
                *act_type = CTC_PORT_SD_ACTION_TYPE_DISCARD_BOTH;
                break;
            default :
                *act_type = CTC_PORT_SD_ACTION_TYPE_NONE;
                break;
        }
    }
    return CTC_E_NONE;
}
STATIC uint8 _sys_usw_port_is_support_glb_port(uint8 lchip)
{
    uint32 cmd = DRV_IOR(EpeHdrAdjustCtl_t, EpeHdrAdjustCtl_cflexGlbDestPortEn_f);
    uint32 field_val = 0;

    DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val);
    if(field_val)
    {
        return 1;
    }

    return 0;

}
int32
_sys_usw_port_map_qos_policy(uint8 lchip, uint32 ctc_qos_trust, uint16 lport)
{
    uint32  cmd = 0;
    DsSrcPort_m ds_src_port;

    cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));
    switch (ctc_qos_trust)
    {
        case CTC_QOS_TRUST_PORT:
            SetDsSrcPort(V, trustOuterPrio_f, &ds_src_port, 0);
            SetDsSrcPort(V, trustPortPcp_f, &ds_src_port, 1);
            break;

        case CTC_QOS_TRUST_OUTER:
            SetDsSrcPort(V, trustOuterPrio_f, &ds_src_port, 1);
            break;

        case CTC_QOS_TRUST_DSCP:
            SetDsSrcPort(V, trustOuterPrio_f, &ds_src_port, 0);
            SetDsSrcPort(V, trustPortPcp_f, &ds_src_port, 0);
            SetDsSrcPort(V, trustDscp_f, &ds_src_port, 1);
            break;

        case CTC_QOS_TRUST_STAG_COS:
        case CTC_QOS_TRUST_COS:
            SetDsSrcPort(V, trustOuterPrio_f, &ds_src_port, 0);
            SetDsSrcPort(V, trustPortPcp_f, &ds_src_port, 0);
            SetDsSrcPort(V, trustDscp_f, &ds_src_port, 0);
            SetDsSrcPort(V, cosPhbUseInner_f, &ds_src_port, 0);
            break;

        case CTC_QOS_TRUST_CTAG_COS:
            SetDsSrcPort(V, trustOuterPrio_f, &ds_src_port, 0);
            SetDsSrcPort(V, trustPortPcp_f, &ds_src_port, 0);
            SetDsSrcPort(V, trustDscp_f, &ds_src_port, 0);
            SetDsSrcPort(V, cosPhbUseInner_f, &ds_src_port, 1);
            break;
        case CTC_QOS_TRUST_IP:
            return CTC_E_NOT_SUPPORT;
        case CTC_QOS_TRUST_MAX:
            return CTC_E_INVALID_PARAM;

        default:
            return CTC_E_INVALID_PARAM;
    }
    cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));
    return CTC_E_NONE;
}

int32
_sys_usw_port_unmap_qos_policy(uint8 lchip, uint16 lport, uint32* ctc_qos_trust)
{
    uint32  cmd = 0;
    DsSrcPort_m  ds_src_port;

    sal_memset(&ds_src_port, 0, sizeof(ds_src_port));

    cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));

    if(GetDsSrcPort(V, trustOuterPrio_f, &ds_src_port))
    {
        *ctc_qos_trust = CTC_QOS_TRUST_OUTER;
    }
    else if(GetDsSrcPort(V, trustPortPcp_f, &ds_src_port))
    {
        *ctc_qos_trust = CTC_QOS_TRUST_PORT;
    }
    else if(GetDsSrcPort(V, trustDscp_f, &ds_src_port))
    {
        *ctc_qos_trust = CTC_QOS_TRUST_DSCP;
    }
    else if(0 == GetDsSrcPort(V, cosPhbUseInner_f, &ds_src_port))
    {
        *ctc_qos_trust = CTC_QOS_TRUST_STAG_COS;
    }
    else if(1 == GetDsSrcPort(V, cosPhbUseInner_f, &ds_src_port))
    {
        *ctc_qos_trust = CTC_QOS_TRUST_CTAG_COS;
    }

    return CTC_E_NONE;
}

/*before xpipe enable: set emac
 *after xpipe enable: set pmac
 */
int32
_sys_usw_port_map_obm_policy(uint8 lchip, uint32 ctc_qos_trust, uint32 gport, uint16 lport)
{
    uint32 pp_id = 0;
    uint32 dp_id = 0;
    uint32 sub_chan = 0;
    uint32 table_index = 0;
    uint32 cmd = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    DsNetRxBufAdmissionCtl_m adm_ctl;

    dmps_port_info.gport = gport;

    if(DRV_FROM_AT(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SUB_CHAN_ID, &sub_chan));
        if (sub_chan >= MCHIP_CAP(SYS_CAP_PER_DP_PHY_CHANNEL_NUM))
        {
            return CTC_E_INVALID_CONFIG;
        }
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, &dp_id));

        lchip = SYS_PP_BASE(lchip) + pp_id;
        cmd = DRV_IOR(DsNetRxChanToPortMap_t, DsNetRxChanToPortMap_portId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &table_index));
    }
    else
    {
        if (p_usw_port_master[lchip]->port_prop[lport].xpipe_type == CTC_PORT_XPIPE_TYPE_0)
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, (void *)&table_index));
            if (table_index >= (MCHIP_CAP(SYS_CAP_MAC_NUM_PER_DP) * MCHIP_CAP(SYS_CAP_DP_MAX_NUM)))
            {
                return CTC_E_INVALID_CONFIG;
            }
        }
        else 
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_GET_PMAC_ID, (void *)&table_index));    
        }
    }

    cmd = DRV_IOR(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, table_index, cmd, &adm_ctl));
    switch (ctc_qos_trust)
    {
        case CTC_QOS_TRUST_PORT:
            SetDsNetRxBufAdmissionCtl(V, cfgForcePort_f, &adm_ctl, 1);
            SetDsNetRxBufAdmissionCtl(V, cfgIpDscpEn_f, &adm_ctl, 0);
            SetDsNetRxBufAdmissionCtl(V, cfgCosEn_f, &adm_ctl, 0);
            break;

        case CTC_QOS_TRUST_DSCP:
            SetDsNetRxBufAdmissionCtl(V, cfgForcePort_f, &adm_ctl, 0);
            SetDsNetRxBufAdmissionCtl(V, cfgIpDscpEn_f, &adm_ctl, 1);
            SetDsNetRxBufAdmissionCtl(V, cfgCosEn_f, &adm_ctl, 0);
            break;

        case CTC_QOS_TRUST_COS:
            SetDsNetRxBufAdmissionCtl(V, cfgForcePort_f, &adm_ctl, 0);
            SetDsNetRxBufAdmissionCtl(V, cfgIpDscpEn_f, &adm_ctl, 0);
            SetDsNetRxBufAdmissionCtl(V, cfgCosEn_f, &adm_ctl, 1);
            break;

        default:
            return CTC_E_INVALID_PARAM;
    }
    cmd = DRV_IOW(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, table_index, cmd, &adm_ctl));

    return CTC_E_NONE;
}

/*before xpipe enable: get emac
 *after xpipe enable: get pmac
 */
int32
_sys_usw_port_unmap_obm_policy(uint8 lchip, uint32 gport, uint16 lport, uint32* ctc_obm_trust)
{
    uint32 pp_id = 0;
    uint32 dp_id = 0;
    uint32 sub_chan = 0;
    uint32 table_index = 0;
    uint32  cmd = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    DsNetRxBufAdmissionCtl_m adm_ctl;

    dmps_port_info.gport = gport;

    if(DRV_FROM_AT(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SUB_CHAN_ID, &sub_chan));
        if (sub_chan >= MCHIP_CAP(SYS_CAP_PER_DP_PHY_CHANNEL_NUM))
        {
            return CTC_E_INVALID_CONFIG;
        }
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, &dp_id));

        lchip = SYS_PP_BASE(lchip) + pp_id;
        cmd = DRV_IOR(DsNetRxChanToPortMap_t, DsNetRxChanToPortMap_portId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &table_index));
    }
    else
    {
        if (p_usw_port_master[lchip]->port_prop[lport].xpipe_type == CTC_PORT_XPIPE_TYPE_0)
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, (void *)&table_index));
            if (table_index >= (MCHIP_CAP(SYS_CAP_MAC_NUM_PER_DP) * MCHIP_CAP(SYS_CAP_DP_MAX_NUM)))
            {
                return CTC_E_INVALID_CONFIG;
            }
        }
        else
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_GET_PMAC_ID, (void *)&table_index));
        }
    }

    cmd = DRV_IOR(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, table_index, cmd, &adm_ctl));
    if(GetDsNetRxBufAdmissionCtl(V, cfgForcePort_f, &adm_ctl))
    {
        *ctc_obm_trust = CTC_QOS_TRUST_PORT;
    }
    else if(GetDsNetRxBufAdmissionCtl(V, cfgIpDscpEn_f, &adm_ctl))
    {
        *ctc_obm_trust = CTC_QOS_TRUST_DSCP;
    }
    else if(GetDsNetRxBufAdmissionCtl(V, cfgCosEn_f, &adm_ctl))
    {
        *ctc_obm_trust = CTC_QOS_TRUST_COS;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_obm_domain(uint8 lchip, uint16 prop, uint32 gport, uint16 lport, uint32 value)
{
    uint32 pp_id = 0;
    uint32 dp_id = 0;
    uint32 sub_chan = 0;
    uint32 table_index = 0;
    uint32 cmd;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    DsNetRxBufAdmissionCtl_m adm_ctl;

    dmps_port_info.gport = gport;

    if(DRV_FROM_AT(lchip))
    {
        dmps_port_info.rx = 1;
        dmps_port_info.index = CTC_MAP_GPORT_TO_MCHAN_IDX(gport);
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SUB_CHAN_ID, &sub_chan));
        if (sub_chan >= MCHIP_CAP(SYS_CAP_PER_DP_PHY_CHANNEL_NUM))
        {
            return CTC_E_INVALID_CONFIG;
        }
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, &dp_id));

        lchip = SYS_PP_BASE(lchip) + pp_id;
        cmd = DRV_IOR(DsNetRxChanToPortMap_t, DsNetRxChanToPortMap_portId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &table_index));
    }
    else
    {
        if (p_usw_port_master[lchip]->port_prop[lport].xpipe_type == CTC_PORT_XPIPE_TYPE_0)
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, (void *)&table_index));
            if (table_index >= (MCHIP_CAP(SYS_CAP_MAC_NUM_PER_DP) * MCHIP_CAP(SYS_CAP_DP_MAX_NUM)))
            {
                return CTC_E_INVALID_CONFIG;
            }
        }
        else 
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_GET_PMAC_ID, (void *)&table_index));
        }
    }

    cmd = DRV_IOR(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, table_index, DRV_CMD_DP_EN(cmd, dp_id), &adm_ctl));

    switch (prop)
    {
        case CTC_PORT_PROP_OBM_DSCP_DOMAIN:
            CTC_MAX_VALUE_CHECK(value, MCHIP_CAP(SYS_CAP_QOS_CLASS_OBM_DSCP_DOMAIN_MAX) - 1);
            SetDsNetRxBufAdmissionCtl(V, cfgIpDscpProfId_f, &adm_ctl, value);
            break;

        case CTC_PORT_PROP_OBM_COS_DOMAIN:
            CTC_MAX_VALUE_CHECK(value, MCHIP_CAP(SYS_CAP_QOS_CLASS_OBM_COS_DOMAIN_MAX) - 1);
            SetDsNetRxBufAdmissionCtl(V, cfgCosProfId_f, &adm_ctl, value);
            break;

        case CTC_PORT_PROP_OBM_DEFAULT_PCP:
            CTC_MAX_VALUE_CHECK(value, MCHIP_CAP(SYS_CAP_QOS_CLASS_OBM_PRIORITY_MAX) - 1);
            SetDsNetRxBufAdmissionCtl(V, cfgPortPri_f, &adm_ctl, value);
            break;

        default:
            return CTC_E_INVALID_PARAM;
    }
    cmd = DRV_IOW(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, table_index, DRV_CMD_DP_EN(cmd, dp_id), &adm_ctl));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_obm_domain(uint8 lchip, uint16 prop, uint32 gport, uint16 lport, uint32* p_value)
{
    uint32 pp_id = 0;
    uint32 dp_id = 0;
    uint32 sub_chan = 0;
    uint32 table_index = 0;
    uint32 cmd;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    DsNetRxBufAdmissionCtl_m adm_ctl;

    dmps_port_info.gport = gport;

    if(DRV_FROM_AT(lchip))
    {
        dmps_port_info.rx = 1;
        dmps_port_info.index = CTC_MAP_GPORT_TO_MCHAN_IDX(gport);
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SUB_CHAN_ID, &sub_chan));
        if (sub_chan >= MCHIP_CAP(SYS_CAP_PER_DP_PHY_CHANNEL_NUM))
        {
            return CTC_E_INVALID_CONFIG;
        }
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, &dp_id));

        lchip = SYS_PP_BASE(lchip) + pp_id;
        cmd = DRV_IOR(DsNetRxChanToPortMap_t, DsNetRxChanToPortMap_portId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &table_index));
    }
    else
    { 
        if (p_usw_port_master[lchip]->port_prop[lport].xpipe_type == CTC_PORT_XPIPE_TYPE_0)
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, (void *)&table_index));
            if (table_index >= (MCHIP_CAP(SYS_CAP_MAC_NUM_PER_DP) * MCHIP_CAP(SYS_CAP_DP_MAX_NUM)))
            {
                return CTC_E_INVALID_CONFIG;
            }
        }
        else 
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_GET_PMAC_ID, (void *)&table_index));
        }
    }

    cmd = DRV_IOR(DsNetRxBufAdmissionCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, table_index, DRV_CMD_DP_EN(cmd, dp_id), &adm_ctl));

    switch (prop)
    {
        case CTC_PORT_PROP_OBM_DSCP_DOMAIN:
            *p_value = GetDsNetRxBufAdmissionCtl(V, cfgIpDscpProfId_f, &adm_ctl);
            break;

        case CTC_PORT_PROP_OBM_COS_DOMAIN:
            *p_value = GetDsNetRxBufAdmissionCtl(V, cfgCosProfId_f, &adm_ctl);
            break;

        case CTC_PORT_PROP_OBM_DEFAULT_PCP:
            *p_value = GetDsNetRxBufAdmissionCtl(V, cfgPortPri_f, &adm_ctl);
            break;

        default:
            return CTC_E_INVALID_PARAM;
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_port_blocking(uint8 lchip, uint32 gport, ctc_port_blocking_pkt_type_t type)
{
    uint16 lport = 0;
    uint32 value = 0;
    uint32 cmd = 0;
    DsDestPort_m ds_dest_port;

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    sal_memset(&ds_dest_port, 0, sizeof(DsDestPort_m));
    cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_dest_port));

    value = CTC_FLAG_ISSET(type, CTC_PORT_BLOCKING_UNKNOW_UCAST) ? 1 : 0;
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "unknown ucast flooding = %d\n", value);
    SetDsDestPort(V, ucastFloodingDisable_f, &ds_dest_port, value);

    value = CTC_FLAG_ISSET(type, CTC_PORT_BLOCKING_UNKNOW_MCAST) ? 1 : 0;
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "unknown mcast flooding = %d\n", value);
    SetDsDestPort(V, mcastFloodingDisable_f, &ds_dest_port, value);

    value = CTC_FLAG_ISSET(type, CTC_PORT_BLOCKING_KNOW_UCAST) ? 1 : 0;
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "known ucast flooding = %d\n", value);
    SetDsDestPort(V, knownUcastFloodingDisable_f, &ds_dest_port, value);

    value = CTC_FLAG_ISSET(type, CTC_PORT_BLOCKING_KNOW_MCAST) ? 1 : 0;
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "known mcast flooding = %d\n", value);
    SetDsDestPort(V, knownMcastFloodingDisable_f, &ds_dest_port, value);

    value = CTC_FLAG_ISSET(type, CTC_PORT_BLOCKING_BCAST) ? 1 : 0;
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "bcast flooding = %d\n", value);
    SetDsDestPort(V, bcastFloodingDisable_f, &ds_dest_port, value);

    cmd = DRV_IOW(DsDestPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_dest_port));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_port_blocking(uint8 lchip, uint32 gport, uint16* p_type)
{
    uint16 lport = 0;
    uint32 value = 0;
    uint32 cmd = 0;
    DsDestPort_m ds_dest_port;

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    sal_memset(&ds_dest_port, 0, sizeof(DsDestPort_m));
    cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_dest_port));

    GetDsDestPort(A, ucastFloodingDisable_f, &ds_dest_port, &value);
    if (value)
    {
        CTC_SET_FLAG(*p_type, CTC_PORT_BLOCKING_UNKNOW_UCAST);
    }

    GetDsDestPort(A, mcastFloodingDisable_f, &ds_dest_port, &value);
    if (value)
    {
        CTC_SET_FLAG(*p_type, CTC_PORT_BLOCKING_UNKNOW_MCAST);
    }

    GetDsDestPort(A, knownUcastFloodingDisable_f, &ds_dest_port, &value);
    if (value)
    {
        CTC_SET_FLAG(*p_type, CTC_PORT_BLOCKING_KNOW_UCAST);
    }

    GetDsDestPort(A, knownMcastFloodingDisable_f, &ds_dest_port, &value);
    if (value)
    {
        CTC_SET_FLAG(*p_type, CTC_PORT_BLOCKING_KNOW_MCAST);
    }

    GetDsDestPort(A, bcastFloodingDisable_f, &ds_dest_port, &value);
    if (value)
    {
        CTC_SET_FLAG(*p_type, CTC_PORT_BLOCKING_BCAST);
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_dump_db(uint8 lchip, sal_file_t dump_db_fp,ctc_global_dump_db_t* p_dump_param)
{
    int32 ret = CTC_E_NONE;
    uint32 lport = 0;

    SYS_DUMP_DB_LOG(dump_db_fp, "\n");
    SYS_DUMP_DB_LOG(dump_db_fp, "%s\n", "# Port");
    SYS_DUMP_DB_LOG(dump_db_fp, "%s\n", "{");
    SYS_DUMP_DB_LOG(dump_db_fp, "%s\n", "Master config:");
    SYS_DUMP_DB_LOG(dump_db_fp, "%s\n", "----------------------------------------------------------------------------------------------------------------------");
    SYS_DUMP_DB_LOG(dump_db_fp, "igs-lport lbk_en    subif_en  xpipe_type  is_mac_da rsv       inter_lport global_src_port nhid\n");

    for (lport =0; lport <SYS_USW_MAX_PORT_NUM_PER_CHIP; lport++)
    {
        SYS_DUMP_DB_LOG(dump_db_fp, "%-10d%-10d%-10d%-12d%-10d%-10d%-12d%-17d%-10u\n",\
        lport,  p_usw_port_master[lchip]->port_prop[lport].lbk_en,\
        p_usw_port_master[lchip]->port_prop[lport].subif_en,\
        p_usw_port_master[lchip]->port_prop[lport].xpipe_type,\
        p_usw_port_master[lchip]->port_prop[lport].is_mac_da,\
        p_usw_port_master[lchip]->port_prop[lport].rsv,\
        p_usw_port_master[lchip]->port_prop[lport].inter_lport,\
        p_usw_port_master[lchip]->port_prop[lport].global_src_port,\
        p_usw_port_master[lchip]->port_prop[lport].nhid);
    }

    SYS_DUMP_DB_LOG(dump_db_fp, "%s\n", "------------------------------------------------------\n");
    SYS_DUMP_DB_LOG(dump_db_fp, "%-30s:%u\n","use_logic_port_check",p_usw_port_master[lchip]->use_logic_port_check);
    SYS_DUMP_DB_LOG(dump_db_fp, "%-30s:%u\n","use_isolation_id",p_usw_port_master[lchip]->use_isolation_id);
    SYS_DUMP_DB_LOG(dump_db_fp, "%-30s:%u\n","isolation_group_mode",p_usw_port_master[lchip]->isolation_group_mode);

    SYS_DUMP_DB_LOG(dump_db_fp, "%-30s:%u\n","igs_isloation_bitmap[0]",p_usw_port_master[lchip]->igs_isloation_bitmap[0]);
    SYS_DUMP_DB_LOG(dump_db_fp, "%-30s:%u\n","igs_isloation_bitmap[1]",p_usw_port_master[lchip]->igs_isloation_bitmap[1]);
    SYS_DUMP_DB_LOG(dump_db_fp, "%-30s:%u\n","opf_type_port_sflow",p_usw_port_master[lchip]->opf_type_port_sflow);

    SYS_DUMP_DB_LOG(dump_db_fp, "%-30s:\n","port reflect bitmap");
    for(lport=0; lport < (SYS_USW_MAX_PORT_NUM_PER_CHIP / BITS_NUM_OF_WORD); lport++)
    {
        SYS_DUMP_DB_LOG(dump_db_fp, "%-31s0x%08x\n"," ",p_usw_port_master[lchip]->reflect_en[lport]);
    }
    SYS_DUMP_DB_LOG(dump_db_fp, "%s\n", "------------------------------------------------------\n");
    SYS_DUMP_DB_LOG(dump_db_fp, "%s\n", "}");

    return ret;
}

STATIC int32
_sys_usw_port_init_opf(uint8 lchip)
{
    sys_usw_opf_t       opf;
    uint8       opf_type_port_sflow = 0;

    sal_memset(&opf, 0, sizeof(sys_usw_opf_t));
    CTC_ERROR_RETURN(sys_usw_opf_init(lchip, &opf_type_port_sflow, CTC_BOTH_DIRECTION, "opf-type-port-sflow"));
    p_usw_port_master[lchip]->opf_type_port_sflow = opf_type_port_sflow;
    /*seed id ingress*/
    opf.pool_index = CTC_INGRESS;
    opf.pool_type  = opf_type_port_sflow;
    CTC_ERROR_RETURN(sys_usw_opf_init_offset(lchip, &opf, 1, 15));
    /*seed id egress*/
    opf.pool_index = CTC_EGRESS;
    opf.pool_type  = opf_type_port_sflow;
    CTC_ERROR_RETURN(sys_usw_opf_init_offset(lchip, &opf, 1, 15));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_seed_id(uint8 lchip, uint16 lport, ctc_direction_t dir, uint8 enable)
{
    sys_usw_opf_t opf;
    uint32      seed_id = 0;
    uint32    tbl_id[CTC_BOTH_DIRECTION] = {0, 0};
    uint32    fld_id[CTC_BOTH_DIRECTION] = {0, 0};
    uint32      cmd = 0;
    uint8       index =  lport;

    if ((lport >= MCHIP_CAP(SYS_CAP_PHY_PORT_NUM_PER_SLICE)) && DRV_IS_TSINGMA(lchip))  /*TM random log seed id only support lport 0-63, other seed id is 0*/
    {
        return CTC_E_NONE;
    }

    tbl_id[CTC_INGRESS] = DRV_FROM_TMM(lchip) ? DsPhyPortExt_t : IpeRandomSeedMap_t;
    fld_id[CTC_INGRESS] = DRV_FROM_TMM(lchip) ? DsPhyPortExt_randomSeedId_f : IpeRandomSeedMap_seedId_f;
    tbl_id[CTC_EGRESS] = DRV_FROM_TMM(lchip) ? DsDestPort_t : EpeRandomSeedMap_t;
    fld_id[CTC_EGRESS] = DRV_FROM_TMM(lchip) ? DsDestPort_randomSeedId_f : EpeRandomSeedMap_seedId_f;

    sal_memset(&opf, 0, sizeof(sys_usw_opf_t));
    opf.pool_index = dir;
    opf.pool_type = p_usw_port_master[lchip]->opf_type_port_sflow;
    if (enable)
    {
        int32 ret = sys_usw_opf_alloc_offset(lchip, &opf, 1, &seed_id);
        if(ret && CTC_E_NO_RESOURCE != ret)
        {
            return ret;
        }
        seed_id = (ret==CTC_E_NO_RESOURCE)?0:seed_id;
    }
    else
    {
        cmd = DRV_IOR(tbl_id[dir], fld_id[dir]);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &seed_id));
        if(seed_id)
        {
            sys_usw_opf_free_offset(lchip, &opf, 1, seed_id);
        }
        seed_id = 0;
    }

    cmd = DRV_IOW(tbl_id[dir], fld_id[dir]);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &seed_id));

    return CTC_E_NONE;
}

int32
sys_usw_port_glb_dest_port_init(uint8 lchip, uint16 glb_port_index)
{
    DsGlbDestPort_m ds_glb_dest_port;
    uint32 cmd = 0;

    sal_memset(&ds_glb_dest_port, 0, sizeof(DsGlbDestPort_m));

    SetDsGlbDestPort(V, defaultVlanId_f, &ds_glb_dest_port, 1);
    SetDsGlbDestPort(V, untagDefaultSvlan_f, &ds_glb_dest_port, 1);
    SetDsGlbDestPort(V, untagDefaultVlanId_f, &ds_glb_dest_port, 1);
    SetDsGlbDestPort(V, bridgeEn_f, &ds_glb_dest_port, 1);
    SetDsGlbDestPort(V, dot1QEn_f, &ds_glb_dest_port, CTC_DOT1Q_TYPE_BOTH);
    SetDsGlbDestPort(V, svlanTpidValid_f, &ds_glb_dest_port, 0);
    SetDsGlbDestPort(V, replaceStagTpid_f, &ds_glb_dest_port, 0);
    SetDsGlbDestPort(V, stagOperationDisable_f, &ds_glb_dest_port, 0);

    cmd = DRV_IOW(DsGlbDestPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, glb_port_index, cmd, &ds_glb_dest_port));


    return CTC_E_NONE;
}

/*NOTE: set global dest port field & clear dest port filed*/
int32 sys_usw_port_set_glb_dest_port_by_dest_port(uint8 lchip, uint16 lport)
{
    uint32 cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
    DsGlbDestPort_m ds_glb_dest_port;
    DsDestPort_m ds_dest_port;

    sal_memset(&ds_dest_port, 0, sizeof(ds_dest_port));
    sal_memset(&ds_glb_dest_port, 0, sizeof(ds_glb_dest_port));

    DRV_IOCTL(lchip, lport, cmd, &ds_dest_port);

    SetDsGlbDestPort(V, bridgeEn_f, &ds_glb_dest_port, GetDsDestPort(V, bridgeEn_f, &ds_dest_port));
    SetDsDestPort(V, bridgeEn_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, cosPhbPtr_f, &ds_glb_dest_port, GetDsDestPort(V, cosPhbPtr_f, &ds_dest_port));
    SetDsDestPort(V, cosPhbPtr_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, ctagOperationDisable_f, &ds_glb_dest_port, GetDsDestPort(V, ctagOperationDisable_f, &ds_dest_port));
    SetDsDestPort(V, ctagOperationDisable_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, cvlanSpace_f, &ds_glb_dest_port, GetDsDestPort(V, cvlanSpace_f, &ds_dest_port));
    SetDsDestPort(V, cvlanSpace_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, defaultDei_f, &ds_glb_dest_port, GetDsDestPort(V, defaultDei_f, &ds_dest_port));
    SetDsDestPort(V, defaultDei_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, defaultDscp_f, &ds_glb_dest_port, GetDsDestPort(V, defaultDscp_f, &ds_dest_port));
    SetDsDestPort(V, defaultDscp_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, defaultPcp_f, &ds_glb_dest_port, GetDsDestPort(V, defaultPcp_f, &ds_dest_port));
    SetDsDestPort(V, defaultPcp_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, defaultVlanId_f, &ds_glb_dest_port, GetDsDestPort(V, defaultVlanId_f, &ds_dest_port));
    SetDsDestPort(V, defaultVlanId_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, dot1QEn_f, &ds_glb_dest_port, GetDsDestPort(V, dot1QEn_f, &ds_dest_port));
    SetDsDestPort(V, dot1QEn_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, dscpPhbPtr_f, &ds_glb_dest_port, GetDsDestPort(V, dscpPhbPtr_f, &ds_dest_port));
    SetDsDestPort(V, dscpPhbPtr_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, dscpRemarkMode_f, &ds_glb_dest_port, GetDsDestPort(V, dscpRemarkMode_f, &ds_dest_port));
    SetDsDestPort(V, dscpRemarkMode_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, priorityTagEn_f, &ds_glb_dest_port, GetDsDestPort(V, priorityTagEn_f, &ds_dest_port));
    SetDsDestPort(V, priorityTagEn_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, replaceCtagCos_f, &ds_glb_dest_port, GetDsDestPort(V, replaceCtagCos_f, &ds_dest_port));
    SetDsDestPort(V, replaceCtagCos_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, replacePortPcp_f, &ds_glb_dest_port, GetDsDestPort(V, replacePortPcp_f, &ds_dest_port));
    SetDsDestPort(V, replacePortPcp_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, replaceStagCos_f, &ds_glb_dest_port, GetDsDestPort(V, replaceStagCos_f, &ds_dest_port));
    SetDsDestPort(V, replaceStagCos_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, replaceStagTpid_f, &ds_glb_dest_port, GetDsDestPort(V, replaceStagTpid_f, &ds_dest_port));
    SetDsDestPort(V, replaceStagTpid_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, stagOperationDisable_f, &ds_glb_dest_port, GetDsDestPort(V, stagOperationDisable_f, &ds_dest_port));
    SetDsDestPort(V, stagOperationDisable_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, svlanTpidIndex_f, &ds_glb_dest_port, GetDsDestPort(V, svlanTpidIndex_f, &ds_dest_port));
    SetDsDestPort(V, svlanTpidIndex_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, svlanTpidValid_f, &ds_glb_dest_port, GetDsDestPort(V, svlanTpidValid_f, &ds_dest_port));
    SetDsDestPort(V, svlanTpidValid_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, untagDefaultSvlan_f, &ds_glb_dest_port, GetDsDestPort(V, untagDefaultSvlan_f, &ds_dest_port));
    SetDsDestPort(V, untagDefaultSvlan_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, untagDefaultVlanId_f, &ds_glb_dest_port, GetDsDestPort(V, untagDefaultVlanId_f, &ds_dest_port));
    SetDsDestPort(V, untagDefaultVlanId_f, &ds_dest_port, 0);

    SetDsGlbDestPort(V, useDecapVlanCos_f, &ds_glb_dest_port, GetDsDestPort(V, useDecapVlanCos_f, &ds_dest_port));
    SetDsDestPort(V, useDecapVlanCos_f, &ds_dest_port, 0);

    cmd = DRV_IOW(DsDestPort_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, lport, cmd, &ds_dest_port);
    cmd = DRV_IOW(DsGlbDestPort_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, lport, cmd, &ds_glb_dest_port);

    return CTC_E_NONE;
}
int32
_sys_usw_port_set_default(uint8 lchip, uint16 start_lport, uint16 end_lport)
{
    DsSrcPort_m ds_src_port;
    DsPhyPort_m ds_phy_port;
    DsDestPort_m ds_dest_port;
    DsGlbDestPort_m ds_glb_dest_port;
    DsPhyPortExt_m ds_phy_port_ext;
    DsPhyPortExt2_m ds_phy_port_ext2;
    DsSrcPortAclCtl_m ds_src_port_acl;
    DsDestPortAclCtl_m ds_dest_port_acl;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    uint32 cmd = 0;
    uint32 gport = 0;
    uint32 val = 0;
    uint8  gchip = 0;
    uint8  support_glb_port = _sys_usw_port_is_support_glb_port(lchip);
    uint32 fwd_ptr = 0;
    uint16 lport = 0;

    sal_memset(&ds_phy_port, 0, sizeof(DsPhyPort_m));
    sal_memset(&ds_phy_port_ext, 0, sizeof(DsPhyPortExt_m));
    sal_memset(&ds_phy_port_ext2, 0, sizeof(DsPhyPortExt2_m));
    sal_memset(&ds_src_port, 0, sizeof(DsSrcPort_m));
    sal_memset(&ds_dest_port, 0, sizeof(DsDestPort_m));
    sal_memset(&ds_glb_dest_port, 0, sizeof(ds_glb_dest_port));
    sal_memset(&ds_src_port_acl, 0, sizeof(DsSrcPortAclCtl_m));
    sal_memset(&ds_dest_port_acl, 0, sizeof(DsDestPortAclCtl_m));

    sys_usw_get_gchip_id(lchip, &gchip);

    if (p_usw_port_master[lchip]->cpu_eth_loop_en)
    {
        /*lport use eth cpu, must set crossconnect*/
        cmd = DRV_IOR(IpePpCtl_t, IpePpCtl_iloopCcDsFwdPtr_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &fwd_ptr));
    }

    SetDsPhyPort(V, microBfdEn_f, &ds_phy_port, 1);
    SetDsPhyPort(V, vlanRangeUntagUseZero1_f, &ds_phy_port, 1);
    SetDsPhyPort(V, vlanRangeUntagUseZero_f, &ds_phy_port, 1);

    SetDsPhyPortExt(V, srcOuterVlanIsSvlan_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, defaultVlanId_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, useDefaultVlanLookup_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, exception2Discard_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, exception2En_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, hash2Priority_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, tcam2Priority_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, hashDefaultEntryValid_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, hash0DefaultEntryValid_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, hash1DefaultEntryValid_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, routerMacLookupEn_f, &ds_phy_port_ext, 1);
    /* SetDsPhyPortExt(V, qosPolicy_f, &ds_phy_port_ext, 1); //default trust port*/
    SetDsPhyPortExt(V, userIdTcamCustomerIdEn_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt2(V, userIdTcamCustomerIdEn_f, &ds_phy_port_ext2, 1);
    SetDsPhyPortExt2(V, mcastVpnLoopback_f, &ds_phy_port_ext2, 1);
    SetDsPhyPortExt2(V, v6McastVpnLoopback_f, &ds_phy_port_ext2, 1);
    SetDsPhyPortExt(V, defaultEntry0Ignore_f, &ds_phy_port_ext, 0);
    SetDsPhyPortExt(V, defaultEntry1Ignore_f, &ds_phy_port_ext, 0);
    SetDsPhyPortExt(V, mcastVpnLoopback_f, &ds_phy_port_ext, 1);
    SetDsPhyPortExt(V, v6McastVpnLoopback_f, &ds_phy_port_ext, 1);
    if(DRV_IS_DUET2(lchip))
    {
        SetDsPhyPortExt(V, userIdTcam1En_f, &ds_phy_port_ext, 1);
        SetDsPhyPortExt(V, userIdTcam1Type_f, &ds_phy_port_ext, TCAMUSERIDKEY);
        SetDsPhyPortExt(V, userIdTcam2En_f, &ds_phy_port_ext, 1);
        SetDsPhyPortExt(V, userIdTcam2Type_f, &ds_phy_port_ext, TCAMUSERIDKEY);
    }

    /*default trust cos*/
    SetDsSrcPort(V, bridgeEn_f, &ds_src_port, 1);
    /* depend on vlan ingress filter */
    SetDsSrcPort(V, ingressFilteringMode_f, &ds_src_port, SYS_PORT_VLAN_FILTER_MODE_VLAN);
    SetDsSrcPort(V, fastLearningEn_f, &ds_src_port, 1);
    SetDsSrcPort(V, isAcOamUseDataVlan_f, &ds_src_port, 1);
    SetDsSrcPort(V, learningDisableMode_f, &ds_src_port, 1);
    SetDsDestPort(V, stpCheckEn_f, &ds_dest_port, 1);
    SetDsDestPort(V, sourcePortToHeader_f, &ds_dest_port, 1);
    SetDsDestPort(V, vlanHash1DefaultEntryValid_f, &ds_dest_port, 1);
    SetDsDestPort(V, vlanHash2DefaultEntryValid_f, &ds_dest_port, 1);
    if(support_glb_port)
    {
        SetDsGlbDestPort(V, defaultVlanId_f, &ds_glb_dest_port, 1);
    }
    else
    {
        SetDsDestPort(V, defaultVlanId_f, &ds_dest_port, 1);
    }
    if(support_glb_port)
    {
        SetDsGlbDestPort(V, untagDefaultSvlan_f, &ds_glb_dest_port, 1);
    }
    else
    {
        SetDsDestPort(V, untagDefaultSvlan_f, &ds_dest_port, 1);
    }
    if(support_glb_port)
    {
        SetDsGlbDestPort(V, untagDefaultVlanId_f, &ds_glb_dest_port, 1);
    }
    else
    {
        SetDsDestPort(V, untagDefaultVlanId_f, &ds_dest_port, 1);
    }
    if(support_glb_port)
    {
        SetDsGlbDestPort(V, bridgeEn_f, &ds_glb_dest_port, 1);
    }
    else
    {
        SetDsDestPort(V, bridgeEn_f, &ds_dest_port, 1);
    }
    if(support_glb_port)
    {
        SetDsGlbDestPort(V, dot1QEn_f, &ds_glb_dest_port, CTC_DOT1Q_TYPE_BOTH);
    }
    else
    {
        SetDsDestPort(V, dot1QEn_f, &ds_dest_port, CTC_DOT1Q_TYPE_BOTH);
    }
    SetDsDestPort(V, isAcOamUseDataVlan_f, &ds_dest_port, 1);
    /*default acl is use gport*/
    SetDsSrcPort(V, gAcl_0_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_1_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_2_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_3_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_4_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_5_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_6_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_7_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_8_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_9_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_10_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_11_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_12_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_13_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_14_aclUseGlobalPortType_f, &ds_src_port, 1);
    SetDsSrcPort(V, gAcl_15_aclUseGlobalPortType_f, &ds_src_port, 1);

    SetDsDestPort(V, gAcl_0_aclUseGlobalPortType_f, &ds_dest_port, 1);
    SetDsDestPort(V, gAcl_1_aclUseGlobalPortType_f, &ds_dest_port, 1);
    SetDsDestPort(V, gAcl_2_aclUseGlobalPortType_f, &ds_dest_port, 1);
    SetDsDestPort(V, gAcl_3_aclUseGlobalPortType_f, &ds_dest_port, 1);

    SetDsDestPort(V, aclQosUseInnerInfo_f, &ds_dest_port, 0);
    SetDsDestPort(V, ipfixUseInnerInfo_f, &ds_dest_port, 0);

    for (lport = start_lport; lport <= end_lport; lport++)
    {
        gport = CTC_MAP_LPORT_TO_GPORT(gchip, lport);

        if (!DRV_FROM_TMM(lchip))
        {
            _sys_usw_port_set_wlan_port_route(lchip, gport, 0);
            _sys_usw_port_set_wlan_port_type(lchip, gport, CTC_PORT_WLAN_PORT_TYPE_NONE);
        }
        if (p_usw_port_master[lchip]->cpu_eth_loop_en && sys_usw_chip_is_eth_cpu_port(lchip, lport))
        {
            /*lport use eth cpu, must set crossconnect*/
            SetDsPhyPortExt(V, u1_g2_dsFwdPtr_f, &ds_phy_port_ext, fwd_ptr);
            SetDsSrcPort(V, portCrossConnect_f, &ds_src_port, 1);
        }
        else
        {
            /*need set 0, if has eth_cpu port*/
            SetDsPhyPortExt(V, u1_g2_dsFwdPtr_f, &ds_phy_port_ext, 0);
            SetDsSrcPort(V, portCrossConnect_f, &ds_src_port, 0);
        }

       if(DRV_IS_DUET2(lchip) || DRV_IS_TSINGMA(lchip))
       {
            if (0 == ((lport >> 7) & 0x1)) /* 0x0xxxxxx*/
            {
                SetDsSrcPort(V, aclPortNum_f, &ds_src_port, lport);
                SetDsDestPort(V, aclPortNum_f, &ds_dest_port, lport);
            }
        }
        else if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
        {
            SetDsSrcPort(V, aclPortNum_f, &ds_src_port, lport);
            SetDsDestPort(V, aclPortNum_f, &ds_dest_port, lport);
        }
        else
        {
            uint16 i = 0;
            SetDsSrcPortAclCtl(V, aclPortNum_f, &ds_src_port_acl, lport);
            for (i = 0; i < MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM); i++)
            {
                SetDsSrcPortAclCtl(V, gAcl_0_aclUseGlobalPortType_f + i, &ds_src_port_acl, 1);
            }
            cmd = DRV_IOW(DsSrcPortAclCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port_acl));

            for (i = 0; i < MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM); i++)
            {
                SetDsDestPortAclCtl(V, gAcl_0_aclUseGlobalPortType_f + i, &ds_dest_port_acl, 1);
            }
            SetDsDestPortAclCtl(V, aclPortNum_f, &ds_dest_port_acl, lport);
            cmd = DRV_IOW(DsDestPortAclCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_dest_port_acl));
        }
        cmd = DRV_IOW(DsPhyPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port));

        cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port_ext));
        cmd = DRV_IOW(DsPhyPortExt2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port_ext2));

        cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));

        cmd = DRV_IOW(DsDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_dest_port));

        cmd = DRV_IOW(DsGlbDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_glb_dest_port));

        dmps_port_info.gport = gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &val));
        cmd = DRV_IOW(DsPortLinkAgg_t, DRV_FROM_TMM(lchip) ? DsPortLinkAgg_channelLinkAggregateGroup_f : DsPortLinkAgg_u1_g2_sourceChannel_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &val));

        sys_usw_port_set_global_port(lchip, SYS_MAP_DRV_LPORT_TO_SYS_LPORT(lport), gport, FALSE);
    }
    return CTC_E_NONE;
}

int32
_sys_usw_port_isolation_type_init(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 index = 0;
    uint32 value = 0;
    DsPortIsolationGroupMapping_m iso_map;

    sal_memset(&iso_map, 0, sizeof(DsPortIsolationGroupMapping_m));
    cmd = DRV_IOW(DsPortIsolationGroupMapping_t, DRV_ENTRY_FLAG);
    /*unknown unicast*/
#if 0
    value = 0;
    SetDsPortIsolationGroupMapping(V, portIsolateType_f, &iso_map, value);
    index = 4;          /*L2UC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 8;          /*MPLS*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 9;          /*VPLS*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 10;          /*L3VPN*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 11;          /*VPWS*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 15;          /*MPLS_OTHER_VPN*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 12;          /*TRILL_UC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 14;          /*FCOE*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
#endif

    /*unknown multicast*/
    value = 1;
    SetDsPortIsolationGroupMapping(V, portIsolateType_f, &iso_map, value);
    index = 5;          /*L2MC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 13;          /*TRILL_MC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));

    /*known unicast*/
    value = 2;
    SetDsPortIsolationGroupMapping(V, portIsolateType_f, &iso_map, value);
    index = (1 << 4) + 4;          /*L2UC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 8;          /*MPLS*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 9;          /*VPLS*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 10;          /*L3VPN*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 11;          /*VPWS*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 15;          /*MPLS_OTHER_VPN*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 12;          /*TRILL_UC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 14;          /*FCOE*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));

    /*known multicast*/
    value = 3;
    SetDsPortIsolationGroupMapping(V, portIsolateType_f, &iso_map, value);
    index = (1 << 4) + 5;          /*L2MC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 13;          /*TRILL_MC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));

    /*bcast*/
    value = 4;
    SetDsPortIsolationGroupMapping(V, portIsolateType_f, &iso_map, value);
    index = 6;          /*BC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));

    if (DRV_FROM_TMM(lchip))
    {
        value = 0;
        index = 7;
        SetDsPortIsolationGroupMapping(V, portIsolateType_f, &iso_map, value);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    }

    /*route*/
    value = 5;
    SetDsPortIsolationGroupMapping(V, portIsolateType_f, &iso_map, value);
    index = 2;          /*IPUC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 2;          /*IPUC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = 3;          /*IPMC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));
    index = (1 << 4) + 3;          /*IPMC*/
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &iso_map));

    return CTC_E_NONE;
}

int32
_sys_usw_port_isolation_init(uint8 lchip, ctc_port_global_cfg_t* p_port_global_cfg)
{
    uint32 cmd = 0;
    uint32 value = 0;
    uint32 value2[CTC_PORT_BITMAP_IN_WORD] = {0};
    MetFifoIsolateCtl_m met_iso_ctl;

    if (!DRV_FROM_TMM(lchip))
    {
        p_usw_port_master[lchip]->isolation_group_mode = p_port_global_cfg->isolation_group_mode;
        value = p_port_global_cfg->isolation_group_mode;
        cmd = DRV_IOW(QWritePortIsolateCtl_t, QWritePortIsolateCtl_portIsolateMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    }

    value = 1;
    cmd = DRV_IOW(QWritePortIsolateCtl_t, QWritePortIsolateCtl_portIsolateFwdTypeEnableBitmap_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    cmd = DRV_IOW(UcQWritePortIsolationCtl_t, UcQWritePortIsolationCtl_portIsolateFwdTypeEnableBitmap_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
    cmd = DRV_IOW(McQWritePortIsolationCtl_t, McQWritePortIsolationCtl_portIsolateFwdTypeEnableBitmap_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

    cmd = DRV_IOR(MetFifoIsolateCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &met_iso_ctl));
    SetMetFifoIsolateCtl(V, peerLink1Valid_f, &met_iso_ctl, 1);
    SetMetFifoIsolateCtl(V, isolationBcastOptimization1_f, &met_iso_ctl, 1);
    SetMetFifoIsolateCtl(V, isolateFwdTypeEnableBitmap1_f, &met_iso_ctl, 1);
    SetMetFifoIsolateCtl(V, bitmap0AsLinkStatus_f, &met_iso_ctl, 1);
    SetMetFifoIsolateCtl(V, isolationBcastOptimization0_f, &met_iso_ctl, 1);
    sal_memset(value2, 0xFF, sizeof(value2));
    SetMetFifoIsolateCtl(A, lagNonBlockBitmap1_f, &met_iso_ctl, value2);
    SetMetFifoIsolateCtl(A, portNonBlockBitmap1_f, &met_iso_ctl, value2);
    SetMetFifoIsolateCtl(A, portNonBlockBitmap0_f, &met_iso_ctl, value2);
    cmd = DRV_IOW(MetFifoIsolateCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &met_iso_ctl));

    p_usw_port_master[lchip]->use_isolation_id =  p_port_global_cfg->use_isolation_id;

    _sys_usw_port_isolation_type_init(lchip);
    return CTC_E_NONE;

}
STATIC int32
_sys_usw_port_wb_init(uint8 lchip)
{
   ctc_wb_appid_t  appid;
   sal_memset(&appid,0,sizeof(appid));

   appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_MASTER) ;
   appid.entry_num = 1;
   appid.entry_size  = sizeof(sys_wb_port_master_t);
   appid.rt_en = 0;
   ctc_wb_add_appid( lchip, &appid);

   appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_MAC_PROP) ;
   appid.entry_num = MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP);
   appid.entry_size  = sizeof(sys_wb_port_mac_prop_t);
   appid.rt_en = 0;
   ctc_wb_add_appid( lchip, &appid);

   appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP) ;
   appid.entry_num = MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP);
   appid.entry_size  = sizeof(sys_wb_port_prop_t);
   appid.rt_en = 0;
   ctc_wb_add_appid( lchip, &appid);

   appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_PORT, SYS_WB_APPID_INTERPORT_SUBID_MASTER) ;
   appid.entry_num = 1;
   appid.entry_size  = sizeof(sys_wb_interport_master_t);
   appid.rt_en = 0;
   ctc_wb_add_appid( lchip, &appid);

   appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_PORT, SYS_WB_APPID_INTERPORT_SUBID_USED) ;
   appid.entry_num = (MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP) / BITS_NUM_OF_WORD)*2;
   appid.entry_size  = sizeof(sys_wb_interport_used_t);
   appid.rt_en = 0;
   ctc_wb_add_appid( lchip, &appid);
   return 0;
}

int32
sys_usw_port_set_default_cfg(uint8 lchip, uint32 gport)
{
    uint32 lport = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X default configure!\n", gport);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    _sys_usw_port_set_default(lchip, lport, lport);

    return CTC_E_NONE;
}
int32
sys_usw_port_get_port_reflective(uint8 lchip, uint32* p_bmp)
{
    sal_memcpy(p_bmp, p_usw_port_master[lchip]->reflect_en, sizeof(p_usw_port_master[lchip]->reflect_en));
    return CTC_E_NONE;
}
int32
sys_usw_port_update_mc_linkagg(uint8 lchip, uint16 tid, uint16 lport, bool is_add)
{
    uint8 mc_port_id = 0;
    uint8 mc_port_type = 0;
    uint32 cmd = 0;
    uint16 bitmap_index = 0;
    uint16 port_index = 0;
    uint32 bmp[4] = {0};
    DsMetLinkAggregatePort_m ds_met_link_aggregate_port;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "tid = %d, lport=%d, is_add=%d\n", tid, lport, is_add);

    SYS_LINKAGG_MC_MAP_PBM_PORTID(lport, mc_port_type, mc_port_id);

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "mc_port_type = %d, mc_port_id=%d\n", mc_port_type, mc_port_id);

    bitmap_index = (tid << 1) + mc_port_type;
    cmd = DRV_IOR(DsMetLinkAggregateBitmap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, bitmap_index, cmd, bmp));

    if (is_add)
    {
        CTC_BMP_SET(bmp, mc_port_id);
    }
    else
    {
        CTC_BMP_UNSET(bmp, mc_port_id);
    }

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "DsMetLinkAggregateBitmap_t index = %d, bmp:0x%x:%x:%x:%x\n",
                        bitmap_index, bmp[3], bmp[2], bmp[1], bmp[0]);


    port_index = DRV_FROM_AT(lchip) ? lport : mc_port_id + (mc_port_type<<7);


    cmd = DRV_IOR(DsMetLinkAggregatePort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, port_index, cmd, &ds_met_link_aggregate_port));

    if (is_add)
    {
        cmd = DRV_IOW(DsMetLinkAggregateBitmap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, bitmap_index, cmd, bmp));

        DRV_SET_FIELD_V(lchip, DsMetLinkAggregatePort_t,
                            DsMetLinkAggregatePort_linkAggregationEn_f,
                            &ds_met_link_aggregate_port,
                            TRUE);

        DRV_SET_FIELD_V(lchip, DsMetLinkAggregatePort_t,
                            DsMetLinkAggregatePort_linkAggregationId_f,
                            &ds_met_link_aggregate_port,
                            tid);

        cmd = DRV_IOW(DsMetLinkAggregatePort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, port_index, cmd, &ds_met_link_aggregate_port));

    }
    else
    {
        DRV_SET_FIELD_V(lchip, DsMetLinkAggregatePort_t,
                            DsMetLinkAggregatePort_linkAggregationEn_f,
                            &ds_met_link_aggregate_port,
                            FALSE);

        DRV_SET_FIELD_V(lchip, DsMetLinkAggregatePort_t,
                            DsMetLinkAggregatePort_linkAggregationId_f,
                            &ds_met_link_aggregate_port,
                            0);

        cmd = DRV_IOW(DsMetLinkAggregatePort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, port_index, cmd, &ds_met_link_aggregate_port));

        cmd = DRV_IOW(DsMetLinkAggregateBitmap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, bitmap_index, cmd, bmp));
    }

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "DsMetLinkAggregatePort_t index = %d\n", port_index);

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_global_port(uint8 lchip, uint16 lport, uint32 gport, bool update_mc_linkagg)
{
    int32  ret = CTC_E_NONE;
    uint32 field_value = 0;
    uint32 cmd = 0;
    uint32 old_gport = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, \
                     "Set Global port, lchip=%u, lport=%u, gport=0x%04X\n", lchip, lport, gport);

    if (SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport) >= SYS_USW_MAX_PORT_NUM_PER_CHIP)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;
    }

    field_value = SYS_MAP_CTC_GPORT_TO_DRV_GPORT(gport);

    /*do write table*/
    cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_globalSrcPort_f);
    ret = DRV_FIELD_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &field_value);

    cmd = DRV_IOW(DsDestPort_t, DsDestPort_globalDestPort_f);
    ret = ret ? ret : DRV_FIELD_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &field_value);

    if (p_usw_port_master[lchip]->use_logic_port_check)
    {
        field_value = 1;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_useDefaultLogicSrcPort_f);
        ret = DRV_FIELD_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &field_value);

        /*for learning use logic port
          Logic port:
          0-(MAX_PORT_NUM_PER_CHIP-1)
              -----------> local phy port
          MAX_PORT_NUM_PER_CHIP - (MAX_PORT_NUM_PER_CHIP+CTC_MAX_LINKAGG_GROUP_NUM-1)
              ---------> linkagg 0-(CTC_MAX_LINKAGG_GROUP_NUM-1), base:MAX_PORT_NUM_PER_CHIP
          MAX_PORT_NUM_PER_CHIP+CTC_MAX_LINKAGG_GROUP_NUM -
              -------> global logic port for userid and vpls learing, base:MAX_PORT_NUM_PER_CHIP+CTC_MAX_LINKAGG_GROUP_NUM
        */
        if (CTC_IS_LINKAGG_PORT(gport))
        {
            field_value = CTC_GPORT_LINKAGG_ID(gport) + SYS_USW_MAX_PORT_NUM_PER_CHIP - 1;
        }
        else
        {
            field_value  = lport;
        }

        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultLogicSrcPort_f);
        ret = DRV_FIELD_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &field_value);

        field_value  = lport;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_logicDestPort_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &field_value);
    }

    CTC_ERROR_RETURN(ret);

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "port_prop[%d].global_src_port(drv_port) = 0x%x.\n", lport, SYS_MAP_CTC_GPORT_TO_DRV_GPORT(gport));

    old_gport = p_usw_port_master[lchip]->port_prop[lport].global_src_port;
    p_usw_port_master[lchip]->port_prop[lport].global_src_port = gport;
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);
    if (CTC_IS_LINKAGG_PORT(gport) && update_mc_linkagg)
    {
        /*update mcast linkagg bitmap*/
        CTC_ERROR_RETURN(sys_usw_port_update_mc_linkagg(lchip, CTC_GPORT_LINKAGG_ID(gport), SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), TRUE));
    }
    else if (CTC_IS_LINKAGG_PORT(old_gport) && update_mc_linkagg)
    {
        /*update mcast linkagg bitmap*/
        CTC_ERROR_RETURN(sys_usw_port_update_mc_linkagg(lchip, CTC_GPORT_LINKAGG_ID(old_gport), SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), FALSE));
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_global_port(uint8 lchip, uint16 lport, uint32 gport, bool update_mc_linkagg)
{
    int32 ret = 0;

    SYS_GLOBAL_PORT_CHECK(gport);
    ret = _sys_usw_port_set_global_port(lchip, lport, gport, update_mc_linkagg);

    return ret;
}

int32
sys_usw_port_get_global_port(uint8 lchip, uint16 lport, uint32* p_gport)
{
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, \
                     "Get Global port, lchip=%d, lport=%d\n", lchip, lport);

    if (SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport) >= SYS_USW_MAX_PORT_NUM_PER_CHIP)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;
    }

    *p_gport = p_usw_port_master[lchip]->port_prop[lport].global_src_port;

    return CTC_E_NONE;
}

int32
_sys_usw_port_set_mcast_member_down(uint8 lchip, uint32 gport, uint8 value)
{
    uint16 lport                   = 0;
    uint32 chan_id                 = 0;
    uint32 cmd                     = 0;
    uint32 field_val               = 0;
    MetFifoIsolateCtl_m     met_fifo_ctl;
    uint32 bitmap[CTC_PORT_BITMAP_IN_WORD]  = {0};
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    CTC_MAX_VALUE_CHECK(value, 1);

    dmps_port_info.gport = gport;
    sal_memset(&met_fifo_ctl, 0, sizeof(met_fifo_ctl));
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOR(MetFifoIsolateCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &met_fifo_ctl));

    GetMetFifoIsolateCtl(A, portNonBlockBitmap0_f, &met_fifo_ctl, bitmap);
    if(value)
    {
        CTC_BMP_UNSET(bitmap, lport);
    }
    else
    {
        CTC_BMP_SET(bitmap, lport);
    }

    SetMetFifoIsolateCtl(A, portNonBlockBitmap0_f, &met_fifo_ctl, bitmap);

    cmd = DRV_IOW(MetFifoIsolateCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &met_fifo_ctl));

    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
    if (SYS_COMMON_USELESS_CHANNEL != chan_id && (DRV_IS_TMM(lchip) || !value))
    {
        field_val = value ? 1 : 0;
        cmd = DRV_IOW(MetFifoLinkStatus_t, MetFifoLinkStatus_linkStatus_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &field_val));
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_port_en(uint8 lchip, uint32 gport, bool enable)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 value = 0;
    uint32 chan_id = 0;
    uint32 port_type = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    EcmpDlbChanStateCtl_m dlb_channel_ctl;
    EcmpDlbLinkState_m dlb_link_state;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X, port enable:%d!\n", gport, enable);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    value = (TRUE == enable) ? 0 : 1;
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_receiveDisable_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));

    value = (TRUE == enable) ? 0 : 1;
    cmd = DRV_IOW(DsDestPort_t, DsDestPort_transmitDisable_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));

    /* clear link status to up*/
    if (TRUE == enable)
    {
        dmps_port_info.gport = gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
        if(SYS_DMPS_NETWORK_PORT == port_type || SYS_DMPS_CPUMAC_NETWORK_PORT == port_type || SYS_DMPS_CPU_MAC_PORT == port_type)
        {
            value = 0;
            sal_memset(&dlb_channel_ctl, 0,sizeof(dlb_channel_ctl));
            cmd = DRV_IOW(LagEngineLinkState_t, LagEngineLinkState_linkState_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &value));
            cmd = DRV_IOW(DlbChanStateCtl_t, DlbChanStateCtl_linkState_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &value));
            SetEcmpDlbChanStateCtl(V, linkState_f, &dlb_channel_ctl, value);
            cmd = DRV_IOW(EcmpDlbChanStateCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, chan_id, cmd, &dlb_channel_ctl));
            SetEcmpDlbLinkState(V, linkState_f, &dlb_link_state, value);
            cmd = DRV_IOW(EcmpDlbLinkState_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, chan_id, cmd, &dlb_link_state));
        }
    }

    CTC_ERROR_RETURN(_sys_usw_port_set_mcast_member_down(lchip, gport, (TRUE == enable) ? 0 : 1));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_port_en(uint8 lchip, uint32 gport, uint32* p_enable)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 receive = 0;
    uint32 transmit = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get gport:0x%04X, port enable!\n", gport);

    CTC_PTR_VALID_CHECK(p_enable);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_receiveDisable_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &receive));

    cmd = DRV_IOR(DsDestPort_t, DsDestPort_transmitDisable_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &transmit));

    if ((0 == receive) && (0 == transmit))
    {
        *p_enable = TRUE;
    }
    else
    {
        *p_enable = FALSE;
    }

    return CTC_E_NONE;
}



STATIC int32
_sys_usw_port_set_cut_through_en(uint8 lchip, uint32 gport,uint32 enable)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 speed = 0;
    uint32 field_val = 0;
    IpeFwdCtl_m ipe_fwd_ctl;
    uint32 cut_through_en[CTC_PORT_BITMAP_IN_WORD] = {0};

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X!\n", gport);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    if (!DRV_FROM_TMM(lchip))
    {
        speed = enable? sys_usw_chip_get_cut_through_speed(lchip, gport) :0;

        field_val = (speed & 0x7);
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_speed_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

        field_val = ((speed>>3)&0x1);
        cmd = DRV_IOW(IpeFwdCtl_t, IpeFwdCtl_gCtSrcportSpeed_0_speedHigherBit_f + lport);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        cmd = DRV_IOW(DsDestPortSpeed_t, DsDestPortSpeed_speed_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &speed));
    }
    else if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
    {
        sal_memset(&ipe_fwd_ctl, 0, sizeof(IpeFwdCtl_m));
        cmd = DRV_IOR(IpeFwdCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));
        GetIpeFwdCtl(A, srcPortCutThroughEn_f, &ipe_fwd_ctl, cut_through_en);
        enable ? CTC_BIT_SET(cut_through_en[lport >> 5], lport & 0x1F) : CTC_BIT_UNSET(cut_through_en[lport >> 5], lport & 0x1F);
        SetIpeFwdCtl(A, srcPortCutThroughEn_f, &ipe_fwd_ctl, cut_through_en);
        cmd = DRV_IOW(IpeFwdCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipe_fwd_ctl));
    }
    else
    {
        IpeFwdSrcPortCtl_m ipefwd_srcport_ctl;
        cmd = DRV_IOR(IpeFwdSrcPortCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipefwd_srcport_ctl));
        GetIpeFwdSrcPortCtl(A, srcPortCutThroughEn_f, &ipefwd_srcport_ctl, cut_through_en);
        enable ? CTC_BIT_SET(cut_through_en[lport >> 5], lport & 0x1F) : CTC_BIT_UNSET(cut_through_en[lport >> 5], lport & 0x1F);
        SetIpeFwdSrcPortCtl(A, srcPortCutThroughEn_f, &ipefwd_srcport_ctl, cut_through_en);
        cmd = DRV_IOW(IpeFwdSrcPortCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ipefwd_srcport_ctl));
    }

    return CTC_E_NONE;
}
STATIC int32
_sys_usw_port_get_cut_through_en(uint8 lchip, uint32 gport,uint32 *enable)
{
    uint32 lport = 0;
    uint32 cmd = 0;
    uint32 speed = 0;
    uint32 cut_through_en[CTC_PORT_BITMAP_IN_WORD] = {0};
    DsDestPortSpeed_m dest_speed;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get gport:0x%04X!\n", gport);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    if (DRV_FROM_AT(lchip))
    {
        cmd = DRV_IOR(IpeFwdSrcPortCtl_t, IpeFwdSrcPortCtl_srcPortCutThroughEn_f);
    }
    else
    {
        cmd = DRV_IOR(IpeFwdCtl_t, IpeFwdCtl_srcPortCutThroughEn_f);
    }

    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, cut_through_en));
    cmd = DRV_IOR(DsDestPortSpeed_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &dest_speed));
    speed = GetDsDestPortSpeed(V, speed_f, &dest_speed);
    *enable = DRV_FROM_TMM(lchip)? (CTC_IS_BIT_SET(cut_through_en[lport>>5], (lport&0x1F))) && speed: (speed != 0);

    return CTC_E_NONE;
}

/**
 @brief decide the port whether is routed port
*/
STATIC int32
_sys_usw_port_set_routed_port(uint8 lchip, uint32 gport, uint32 is_routed)
{

    int32 ret = CTC_E_NONE;

    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 field_value = (TRUE == is_routed) ? 1 : 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X, routed port:%d!\n", gport, is_routed);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    /*do write table*/
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_routedPort_f);
    ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

    cmd = DRV_IOW(DsDestPort_t, DsDestPort_routedPort_f);
    ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

    return ret;
}

/**
 @brief get the port whether is routed port
*/
STATIC int32
_sys_usw_port_get_routed_port(uint8 lchip, uint32 gport, bool* p_is_routed)
{
    int32 ret = CTC_E_NONE;

    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 value1 = 0;
    uint32 value2 = 0;

    CTC_PTR_VALID_CHECK(p_is_routed);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get gport:0x%04X!\n", gport);

    /*do write table*/
    cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_routedPort_f);
    ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &value1);

    cmd = DRV_IOR(DsDestPort_t, DsDestPort_routedPort_f);
    ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &value2);

    if (value1 && value2)
    {
        *p_is_routed = TRUE;
    }
    else
    {
        *p_is_routed = FALSE;
    }

    return ret;
}

int32
sys_usw_port_set_phy_if_en(uint8 lchip, uint32 gport, bool enable)
{
    int32  ret = CTC_E_NONE;

    uint16 lport = 0;
    uint32 field_value = 0;
    uint32 cmd = 0;
    uint32 is_phy = FALSE;
    uint16 global_src_port = 0;
    sys_l3if_brief_info_t l3if_prop;
    uint8  is_support_glb_port = _sys_usw_port_is_support_glb_port(lchip);
    uint8   gchip = SYS_MAP_CTC_GPORT_TO_GCHIP(gport);
    bool is_routed_port = FALSE;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X, phy_if enable:%d\n", gport, enable);

    /*Sanity check*/
    SYS_GLOBAL_CHIPID_CHECK(gchip);
    if (FALSE == sys_usw_chip_is_local(lchip, gchip))
    {
        if(!is_support_glb_port || !p_usw_port_master[lchip]->rchip_gport_idx_cb)
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "the callback function for mapping gport to global dest index is not registered!\n");
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " API or some feature is not supported \n");
            return CTC_E_INVALID_CONFIG;
        }
        CTC_ERROR_RETURN(p_usw_port_master[lchip]->rchip_gport_idx_cb(lchip, gport, &lport));
    }
    else
    {
        lport = CTC_MAP_GPORT_TO_LPORT(gport);
    }

    global_src_port = p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(gport)].global_src_port;
    sal_memset(&l3if_prop, 0, sizeof(sys_l3if_brief_info_t));

    l3if_prop.gport = global_src_port;
    l3if_prop.l3if_type = CTC_L3IF_TYPE_PHY_IF;
    l3if_prop.vaild     = 1;

    is_phy = sys_usw_l3if_is_port_phy_if(lchip, sys_usw_chip_is_local(lchip, gchip)? global_src_port: gport);
    if ((TRUE == enable) && (FALSE == is_phy))
    {
        return CTC_E_NOT_EXIST;
    }
    /* ecmp if only support egress edit mode when create l3if with bind_en indicate interface used as ecmp interface member, 
      but don't have phy interface property actual is vlan interface */
    if (sys_usw_chip_is_local(lchip, gchip))
    {
        if (enable)
        {
            CTC_ERROR_RETURN(sys_usw_l3if_get_l3if_brief_info(lchip, &l3if_prop));
            if(l3if_prop.bind_en)
            {
                field_value = l3if_prop.l3if_id;
                cmd = DRV_IOW(DsDestPort_t, DsDestPort_portMappedInterfaceId_f);
                ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);
                return ret;
            }
        }
        else
        {
            CTC_ERROR_RETURN(_sys_usw_port_get_routed_port(lchip, gport, &is_routed_port));
            if(FALSE == is_routed_port)
            {
                field_value = 0;
                cmd = DRV_IOW(DsDestPort_t, DsDestPort_portMappedInterfaceId_f);
                ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);
                return ret;
            }
        }
    }
    /* cfg phy interface remote property */
    field_value = ((TRUE == enable)? 0: CTC_DOT1Q_TYPE_BOTH);
    cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dot1QEn_f) : DRV_IOW(DsDestPort_t, DsDestPort_dot1QEn_f);
    ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

    field_value = ((TRUE == enable)? 0: 1);
    cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultVlanId_f) : DRV_IOW(DsDestPort_t, DsDestPort_defaultVlanId_f);
    ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);
    cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_bridgeEn_f) : DRV_IOW(DsDestPort_t, DsDestPort_bridgeEn_f);
    ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);
    if (FALSE == sys_usw_chip_is_local(lchip, gchip))
    {
        return ret;
    }

#if 0 /*allow destroy interfaced first, then disable in port*/
    if ((FALSE == enable) && (TRUE == is_phy))
    {
        return CTC_E_EXIST;
    }

#endif
    if (TRUE == enable)
    {
        ret = _sys_usw_port_set_routed_port(lchip, gport, TRUE);

        field_value = l3if_prop.l3if_id;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_interfaceId_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        field_value = 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_addDefaultVlanDisable_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        field_value = 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_stpDisable_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        field_value = 0;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultVlanId_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        /* enable phy if should disable bridge */
        field_value = 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_bridgeEn_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        field_value = l3if_prop.l3if_id;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_portMappedInterfaceId_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);
    }
    else
    {
        ret = _sys_usw_port_set_routed_port(lchip, gport, FALSE);

        field_value = 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_interfaceId_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        field_value = 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_addDefaultVlanDisable_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        field_value = 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_stpDisable_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        field_value = 1;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultVlanId_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        /* disable phy if should enable bridge */
        field_value = 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_bridgeEn_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);

        field_value = 0;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_portMappedInterfaceId_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value);
    }
    return ret;
}

int32
sys_usw_port_get_phy_if_en(uint8 lchip, uint32 gport, uint16* p_l3if_id, bool* p_enable)
{
    bool   is_routed = FALSE;

    int32  ret = CTC_E_NONE;
    uint16 lport = 0;
    uint32 value = 0;
    uint32 cmd = 0;
    DsSrcPort_m ds_src_port;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get gport:0x%04X, phyical interface!\n", gport);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    CTC_ERROR_RETURN(_sys_usw_port_get_routed_port(lchip, gport, &is_routed));

    if (TRUE == is_routed)
    {
        *p_enable = TRUE;
    }
    else
    {
        *p_enable = FALSE;
    }

    sal_memset(&ds_src_port, 0, sizeof(DsSrcPort_m));
    cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));

    GetDsSrcPort(A, interfaceId_f, &ds_src_port, &value);
    *p_l3if_id = value;

    return ret;
}

int32
sys_usw_port_set_vlan_range(uint8 lchip, uint32 gport, ctc_vlan_range_info_t* p_vrange_info, bool is_svlan, bool enable)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint8 direcion = p_vrange_info->direction;
    uint8 block_id = p_vrange_info->block_id;
    uint32 vlan_range_profile_en[] = {DsPhyPort_vlanRangeProfileEn_f, DsPhyPort_vlanRangeProfileEn1_f};
    uint32 vlan_range_type[] = {DsPhyPort_vlanRangeType_f, DsPhyPort_vlanRangeType1_f};
    uint32 vlan_range_profile[] = {DsPhyPort_vlanRangeProfile_f, DsPhyPort_vlanRangeProfile1_f};

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X, block_id:%d,direction:%d, vrange_grpid:%d\n",
                     gport, p_vrange_info->block_id, p_vrange_info->direction, p_vrange_info->vrange_grpid);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    if (CTC_INGRESS == direcion)
    {
        if (!enable)
        {
            field_val = 0;
            cmd = DRV_IOW(DsPhyPort_t, vlan_range_profile_en[block_id]);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
        }
        else
        {
            if (is_svlan)
            {
                field_val = 1;
            }
            else
            {
                field_val = 0;
            }

            cmd = DRV_IOW(DsPhyPort_t, vlan_range_type[block_id]);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

            field_val = 1;
            cmd = DRV_IOW(DsPhyPort_t, vlan_range_profile_en[block_id]);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

            field_val = p_vrange_info->vrange_grpid;
            cmd = DRV_IOW(DsPhyPort_t, vlan_range_profile[block_id]);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
        }
    }
    else
    {
        if (!enable)
        {
            field_val = 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_vlanRangeProfileEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
        }
        else
        {
            if (is_svlan)
            {
                field_val = 1;
            }
            else
            {
                field_val = 0;
            }

            cmd = DRV_IOW(DsDestPort_t, DsDestPort_vlanRangeType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

            field_val = 1;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_vlanRangeProfileEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

            field_val = p_vrange_info->vrange_grpid;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_vlanRangeProfile_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
        }
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_get_vlan_range(uint8 lchip, uint32 gport, ctc_vlan_range_info_t* p_vrange_info, bool* p_enable)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint8 direction = p_vrange_info->direction;
    uint8 block_id = p_vrange_info->block_id;
    uint32 vlan_range_profile_en[] = {DsPhyPort_vlanRangeProfileEn_f, DsPhyPort_vlanRangeProfileEn1_f};
    uint32 vlan_range_profile[] = {DsPhyPort_vlanRangeProfile_f, DsPhyPort_vlanRangeProfile1_f};
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get gport:0x%04X, vlan range!\n", gport);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    if (CTC_INGRESS == direction)
    {
        cmd = DRV_IOR(DsPhyPort_t, vlan_range_profile_en[block_id]);

        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
        if (0 == field_val)
        {
            *p_enable = FALSE;
        }
        else
        {
            cmd = DRV_IOR(DsPhyPort_t, vlan_range_profile[block_id]);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
            p_vrange_info->vrange_grpid = field_val;
            *p_enable = TRUE;
        }
    }
    else
    {
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_vlanRangeProfileEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
        if (0 == field_val)
        {
            *p_enable = FALSE;
        }
        else
        {
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_vlanRangeProfile_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
            p_vrange_info->vrange_grpid = field_val;
            *p_enable = TRUE;
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_scl_key_type_ingress(uint8 lchip, uint16 lport, uint8 scl_id, ctc_port_scl_key_type_t type)
{
    DsPhyPortExt_m ds;
    DsPhyPortExt2_m ds2;
    uint32 cmd = 0;

    sys_usw_igs_port_scl_map_t scl_map[CTC_SCL_KEY_TYPE_MAX] =
    {
        /* hash_type                       , tcam_type   ,en,high,ul,lab,ad,da,v4,gre,rpf,auto,nvgre,v6_nvgre,v4_vxlan,v6_vxlan*/
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_DISABLE)        , TCAMDISABLE , 0, 0 , 0 , 0 , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_DISABLE                */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_PORT)           , TCAML2KEY   , 1, 0 , 0 , 0 , 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_MAPPING_PORT      */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_CVLANPORT)      , TCAML2KEY   , 1, 0 , 0 , 0 , 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_MAPPING_CVID      */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_SVLANPORT)      , TCAML2KEY   , 1, 0 , 0 , 0 , 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_MAPPING_SVID      */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_CVLANCOSPORT)   , TCAML2KEY   , 1, 0 , 0 , 0 , 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_MAPPING_CVID_CCOS */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_SVLANCOSPORT)   , TCAML2KEY   , 1, 0 , 0 , 0 , 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_MAPPING_SVID_SCOS */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_DOUBLEVLANPORT) , TCAML2KEY   , 1, 0 , 0 , 0 , 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_MAPPING_DVID      */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_MAC)            , TCAML2KEY   , 1, 1 , 1 , 62, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_CLASS_MAC_SA      */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_MAC)            , TCAML2KEY   , 1, 1 , 1 , 62, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_CLASS_MAC_DA      */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_IPSA)           , TCAML3KEY   , 1, 1 , 1 , 62, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_CLASS_IPV4        */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_IPSA)           , TCAML3KEY   , 1, 1 , 1 , 62, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_VLAN_CLASS_IPV6        */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_MACPORT)        , TCAML2KEY   , 1, 1 , 0 , 63, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_IPSG_PORT_MAC          */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_IPSAPORT)       , TCAML3KEY   , 1, 1 , 0 , 63, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_IPSG_PORT_IP           */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_IPSA)           , TCAML3KEY   , 1, 1 , 0 , 63, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_IPSG_IPV6              */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL)         , TCAML3KEY   , 1, 0 , 0 , 0 , 0, 0, 1, 1, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_IPV4_TUNNEL            */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL)         , TCAML3KEY   , 1, 0 , 0 , 0 , 0, 0, 1, 1, 0, 1, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_IPV4_TUNNEL_AUTO       */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL)         , TCAML3KEY   , 1, 0 , 0 , 0 , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_IPV6_TUNNEL            */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL)         , TCAML3KEY   , 1, 0 , 0 , 0 , 0, 0, 1, 1, 1, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_IPV4_TUNNEL_WITH_RPF   */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL)         , TCAML3KEY   , 1, 0 , 0 , 0 , 0, 0, 0, 0, 1, 0, 0, 0, 0, 0} , /*CTC_SCL_KEY_TYPE_IPV6_TUNNEL_WITH_RPF   */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL)         , TCAML3KEY   , 1, 0 , 0 , 0 , 0, 0, 0, 1, 0, 0, 1, 1, 0, 0} , /*CTC_SCL_KET_TYPE_NVGRE                  */
        {DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL)         , TCAML3KEY   , 1, 0 , 0 , 0 , 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} , /*CTC_SCL_KET_TYPE_VXLAN                  */
    };

    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &ds));
    cmd = DRV_IOR(DsPhyPortExt2_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &ds2));

    if (CTC_SCL_KEY_TYPE_IPV4_TUNNEL_WITH_RPF == type)
    {
        if (0 == scl_id)
        {
            return CTC_E_INVALID_PARAM;
        }
    }

    if (CTC_SCL_KEY_TYPE_IPV6_TUNNEL_WITH_RPF == type)
    {
        if (0 == scl_id)
        {
            return CTC_E_INVALID_PARAM;
        }
    }

    if (0 == scl_id)
    {
        SetDsPhyPortExt(V, hash1UseDa_f, &ds, scl_map[type].use_macda);
        SetDsPhyPortExt(V, userIdPortHash1Type_f, &ds, scl_map[type].hash_type);
        SetDsPhyPortExt(V, userIdTcam1En_f, &ds, scl_map[type].tcam_en);
        SetDsPhyPortExt(V, userIdTcam1Type_f, &ds, scl_map[type].tcam_type);
        SetDsPhyPortExt(V, hashLookup1UseLabel_f , &ds, scl_map[type].use_label);
        SetDsPhyPortExt(V, userIdLabel1_f, &ds, scl_map[type].label);

        SetDsPhyPortExt(V, ipv4TunnelHashEn1_f, &ds, scl_map[type].ipv4_tunnel_en);
        SetDsPhyPortExt(V, ipv4GreTunnelHashEn1_f, &ds, scl_map[type].ipv4_gre_tunnel_en);
        SetDsPhyPortExt(V, autoTunnelEn_f, &ds, scl_map[type].auto_tunnel);
        SetDsPhyPortExt(V, autoTunnelForHash1_f, &ds, scl_map[type].auto_tunnel);
        SetDsPhyPortExt(V, nvgreEnable_f, &ds, scl_map[type].nvgre_en);
        SetDsPhyPortExt(V, ipv4VxlanTunnelHashEn1_f, &ds, scl_map[type].v4_vxlan_en);
        SetDsPhyPortExt(V, ipv6NvgreTunnelHashEn1_f, &ds, scl_map[type].v6_nvgre_en);
        SetDsPhyPortExt(V, ipv6VxlanTunnelHashEn1_f, &ds, scl_map[type].v6_vxlan_en);

        SetDsPhyPortExt(V, tcam1IsUserId_f, &ds, scl_map[type].is_userid);
        SetDsPhyPortExt(V, tcam1IsSclFlow_f, &ds, 0);
        SetDsPhyPortExt(V, sclFlowHashEn_f , &ds, 0);

        SetDsPhyPortExt2(V, hash0UseDa_f, &ds2, scl_map[type].use_macda);
        SetDsPhyPortExt2(V, userIdPortHash0Type_f, &ds2, scl_map[type].hash_type);
        SetDsPhyPortExt2(V, hashLookup0UseLabel_f , &ds2, scl_map[type].use_label);
        SetDsPhyPortExt2(V, userIdLabel0_f, &ds2, scl_map[type].label);

        SetDsPhyPortExt2(V, ipv4TunnelHashEn0_f, &ds2, scl_map[type].ipv4_tunnel_en);
        SetDsPhyPortExt2(V, ipv4GreTunnelHashEn0_f, &ds2, scl_map[type].ipv4_gre_tunnel_en);
        SetDsPhyPortExt2(V, autoTunnelEn_f, &ds2, scl_map[type].auto_tunnel);
        SetDsPhyPortExt2(V, autoTunnelForHash0_f, &ds2, scl_map[type].auto_tunnel);
        SetDsPhyPortExt2(V, nvgreEnable_f, &ds, scl_map[type].nvgre_en);
        SetDsPhyPortExt2(V, ipv4VxlanTunnelHashEn0_f, &ds2, scl_map[type].v4_vxlan_en);
        SetDsPhyPortExt2(V, ipv6NvgreTunnelHashEn0_f, &ds2, scl_map[type].v6_nvgre_en);
        SetDsPhyPortExt2(V, ipv6VxlanTunnelHashEn0_f, &ds2, scl_map[type].v6_vxlan_en);
    }

    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &ds));
    cmd = DRV_IOW(DsPhyPortExt2_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &ds2));
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_ingressTagHighPriority_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport), cmd, &scl_map[type].vlan_high_priority));
    return CTC_E_NONE;
}

int32
sys_usw_port_set_sub_if_en(uint8 lchip, uint32 gport, bool enable)
{
    uint16 lport = 0;
    uint32 is_sub = FALSE;
    uint16 global_src_port = 0;
    uint8 double_vlan = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X, phy_if enable:%d\n", gport, enable);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    global_src_port = p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(gport)].global_src_port;

    is_sub = sys_usw_l3if_is_port_sub_if(lchip, global_src_port, &double_vlan);

    if ((TRUE == enable) && (FALSE == is_sub))
    {
        return CTC_E_NOT_EXIST;
    }
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);
    if (TRUE == enable)
    {
        CTC_ERROR_RETURN(_sys_usw_port_set_scl_key_type_ingress(lchip, CTC_MAP_GPORT_TO_LPORT(gport), 0, 
                         double_vlan? CTC_SCL_KEY_TYPE_VLAN_MAPPING_DVID : CTC_SCL_KEY_TYPE_VLAN_MAPPING_SVID));
        p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(gport)].subif_en = TRUE;
    }
    else if (p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(gport)].subif_en)
    {
        CTC_ERROR_RETURN(_sys_usw_port_set_scl_key_type_ingress(lchip, CTC_MAP_GPORT_TO_LPORT(gport), 0, CTC_SCL_KEY_TYPE_DISABLE));
        p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(gport)].subif_en = FALSE;
    }

    return CTC_E_NONE;
}

int32
_sys_usw_port_get_use_logic_port(uint8 lchip, uint32 gport, uint8* enable, uint32* logicport)
{
    uint16 lport = 0;
    uint32 field_value = 0;
    uint32 cmd = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    lport = CTC_MAP_GPORT_TO_LPORT(gport);
    *enable = p_usw_port_master[lchip]->use_logic_port_check;
    if (p_usw_port_master[lchip]->use_logic_port_check)
    {
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_defaultLogicSrcPort_f);
        CTC_ERROR_RETURN((DRV_FIELD_IOCTL(lchip, lport, cmd, &field_value)));
        *logicport = field_value;
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_get_sub_if_en(uint8 lchip, uint32 gport,  bool* p_enable)
{
    uint16 lport = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    *p_enable = p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(gport)].subif_en;
    return CTC_E_NONE;
}

int32
_sys_usw_port_maping_to_local_phy_port(uint8 lchip, uint32 gport, uint16 local_phy_port)
{
    uint32 cmd = 0;
    uint32 field_value = local_phy_port;
    uint32 chan = 0;
    uint32 chan_id[SYS_USW_MAX_CHANEL_NUM_PER_PORT] = {0};
    uint8 chan_num = 0;

    CTC_ERROR_RETURN(sys_usw_port_get_channel(lchip, 1, gport, chan_id, &chan_num));
    if (DRV_FROM_AT(lchip) && 0 == chan_num)
    {
        chan_num = 1;
    }
    chan =DRV_IS_TSINGMA(lchip)? (chan_id[0]):(chan_id[chan_num-1]);
    if ( chan >= MCHIP_CAP(SYS_CAP_CHANID_MAX))
    {
        return CTC_E_INVALID_PORT;
    }

    cmd = DRV_IOW(IpeHeaderAdjustPhyPortMap_t, IpeHeaderAdjustPhyPortMap_localPhyPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan, cmd, &field_value));

    return CTC_E_NONE;
}

int32
_sys_usw_port_set_lbk_port_property(uint8 lchip, ctc_port_lbk_param_t* p_port_lbk, uint16 inter_lport, uint16 dsfwd_offset)
{


    uint8  enable = 0;
    uint16 src_lport = 0;
    uint16 inter_dlport = 0;
    uint32 src_gport = 0;
    uint32 cmd = 0;
    DsPhyPortExt_m inter_phy_port_ext;
    DsSrcPort_m inter_src_port;
    DsDestPort_m inter_dest_port;

    CTC_PTR_VALID_CHECK(p_port_lbk);
    enable = p_port_lbk->lbk_enable ? 1 : 0;
    src_gport = p_port_lbk->src_gport;
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(src_gport, lchip, src_lport);
    inter_dlport = SYS_MAP_SYS_LPORT_TO_DRV_LPORT(inter_lport);

    sal_memset(&inter_src_port,     0, sizeof(DsSrcPort_m));
    sal_memset(&inter_dest_port,    0, sizeof(DsDestPort_m));
    sal_memset(&inter_phy_port_ext, 0, sizeof(DsPhyPortExt_m));

    cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_dlport, cmd, &inter_src_port));

    SetDsSrcPort(V, portCrossConnect_f, &inter_src_port, (enable ? 1 : 0));
    SetDsSrcPort(V, receiveDisable_f, &inter_src_port, 0);
    SetDsSrcPort(V, stpDisable_f, &inter_src_port, (enable ? 1 : 0));
    SetDsSrcPort(V, addDefaultVlanDisable_f, &inter_src_port, (enable ? 1 : 0));
    SetDsSrcPort(V, routeDisable_f, &inter_src_port, (enable ? 1 : 0));
    SetDsSrcPort(V, learningDisable_f, &inter_src_port, (enable ? 1 : 0));
    SetDsSrcPort(V, ingressFilteringMode_f, &inter_src_port, SYS_PORT_VLAN_FILTER_MODE_VLAN);

    /*l2pdu same to src port*/
    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_dlport, cmd, &inter_phy_port_ext));

    cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_dlport, cmd, &inter_dest_port));

    SetDsPhyPortExt(V, u1_g2_dsFwdPtr_f, &inter_phy_port_ext, dsfwd_offset);

    if (enable)
    {
        SetDsSrcPort(V, bridgeEn_f, &inter_src_port, 0);
        SetDsPhyPortExt(V, defaultVlanId_f, &inter_phy_port_ext, 0);
        SetDsDestPort(V, stpCheckEn_f, &inter_dest_port, 0);
        if ((p_port_lbk->src_gport == p_port_lbk->dst_gport) && p_port_lbk->lbk_mode)
        {
            SetDsPhyPortExt(V, efmLoopbackEn_f, &inter_phy_port_ext, 1);
            SetDsDestPort(V, discardNon8023Oam_f, &inter_dest_port, 1);
        }
    }
    else
    {
        SetDsSrcPort(V, bridgeEn_f, &inter_src_port, 1);
        SetDsPhyPortExt(V, exception2En_f, &inter_phy_port_ext, 0);
        SetDsPhyPortExt(V, exception2Discard_f, &inter_phy_port_ext, 0);
        SetDsPhyPortExt(V, efmLoopbackEn_f, &inter_phy_port_ext, 0);
        SetDsPhyPortExt(V, defaultVlanId_f, &inter_phy_port_ext, 1);
        SetDsDestPort(V, discardNon8023Oam_f, &inter_dest_port, 0);
        SetDsDestPort(V, reflectiveBridgeEn_f, &inter_dest_port, (enable ? 1 : 0));
        SetDsDestPort(V, egressFilteringMode_f, &inter_dest_port, SYS_PORT_VLAN_FILTER_MODE_VLAN);
        SetDsDestPort(V, stpCheckEn_f, &inter_dest_port, 1);
    }

    cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_dlport, cmd, &inter_src_port));

    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_dlport, cmd, &inter_phy_port_ext));

    cmd = DRV_IOW(DsDestPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_dlport, cmd, &inter_dest_port));

    return CTC_E_NONE;

}

STATIC int32
_sys_usw_port_set_cross_connect(uint8 lchip, uint32 cc_gport, uint32 nhid)
{
    uint16  lport = 0;
    uint32  cmd = 0;
    uint32  field_val = 0;
    bool enable = FALSE;
    uint32 dsfwd_offset = 0;
    sys_nh_info_dsnh_t nhinfo;

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(cc_gport, lchip, lport);

    /* when efm loopback enabled on src port, cc should not be enabled.*/
    if (p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(cc_gport)].lbk_en)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Has other feature on this port \n");
        return CTC_E_INVALID_CONFIG;

    }

    sal_memset(&nhinfo, 0, sizeof(nhinfo));
    if(SYS_NH_INVALID_NHID != nhid)
    {
        CTC_ERROR_RETURN(sys_usw_nh_get_nhinfo(lchip, nhid, &nhinfo, 0));
        if((nhinfo.ecmp_valid) && (DRV_FROM_AT(lchip)))
        {
            dsfwd_offset = nhinfo.ecmp_group_id;
            enable = TRUE;
        }
        else
        {
            CTC_ERROR_RETURN(sys_usw_nh_get_dsfwd_offset(lchip, nhid, &dsfwd_offset, 0, CTC_FEATURE_PORT));
            enable = TRUE;
        }
    }

    field_val = enable ? 1 : 0;
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portCrossConnect_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

    field_val = enable ? 0 : 1;
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_bridgeEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));


    field_val = enable ? 1 : 0;
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_routedPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

    field_val = enable ? 1 : 0;
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_addDefaultVlanDisable_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

    field_val = enable ? 1 : 0;
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_learningDisable_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

    field_val = nhinfo.ecmp_valid;
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portCrossConnetIsEcmp_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

    p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(cc_gport)].nhid = nhid;
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_cross_connect(uint8 lchip, uint32 cc_gport, uint32* p_value)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 bridge_en = 0;
    uint32 port_cross_connect = 0;

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(cc_gport, lchip, lport);

    cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_bridgeEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &bridge_en));

    cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portCrossConnect_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &port_cross_connect));

    if ((0 == bridge_en) && (1 == port_cross_connect))
    {
        *p_value = p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(cc_gport)].nhid;
    }
    else
    {
        *p_value = SYS_NH_INVALID_NHID;
    }

    return CTC_E_NONE;
}

/* efm and crossconnect loopback */
STATIC int32
_sys_usw_port_set_loopback(uint8 lchip, ctc_port_lbk_param_t* p_port_lbk)
{
    uint16  sys_internal_gport = 0;
    uint16  sys_internal_lport = 0;
    uint16  drv_internal_lport = 0;
    uint16  drv_src_lport = 0;
    uint32  sys_src_gport   = 0;
    uint32  sys_dst_gport   = 0;
    uint32  dsfwd_offset = 0;
    uint32  nhid        = 0;
    uint8   gchip       = 0;
    uint32   chan        = 0;

    int32  ret         = CTC_E_NONE;
    ctc_misc_nh_param_t nh_param;
    ctc_internal_port_assign_para_t port_assign;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

#define RET_PROCESS_WITH_ERROR(func) ret = ret ? ret : (func)

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    sys_src_gport = p_port_lbk->src_gport;
    sys_dst_gport = p_port_lbk->dst_gport;

    /*not support linkagg*/
    if (CTC_IS_LINKAGG_PORT(sys_src_gport))
    {
        return CTC_E_INVALID_PARAM;
    }

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(sys_src_gport, lchip, drv_src_lport);

    gchip = CTC_MAP_GPORT_TO_GCHIP(sys_src_gport);
    SYS_GLOBAL_CHIPID_CHECK(gchip);
    sal_memset(&nh_param,   0, sizeof(ctc_misc_nh_param_t));
    sal_memset(&port_assign,    0, sizeof(ctc_internal_port_assign_para_t));


    CTC_ERROR_RETURN(_sys_usw_port_get_cross_connect(lchip, sys_src_gport, &nhid));

    /* cc is enabled on src port */
    if (SYS_NH_INVALID_NHID != nhid)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Has other feature on this port \n");
        return CTC_E_INVALID_CONFIG;

    }

    nhid = 0;

    if (p_port_lbk->lbk_enable)
    {
        if (p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].lbk_en)
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Entry already exist \n");
            return CTC_E_EXIST;

        }

        /* allocate internal port */
        port_assign.type        = CTC_INTERNAL_PORT_TYPE_FWD;
        port_assign.gchip       = gchip;
        if (CTC_PORT_LBK_MODE_EFM == p_port_lbk->lbk_mode)
        {
            port_assign.fwd_gport       = sys_src_gport;
        }
        else if(CTC_PORT_LBK_MODE_CC == p_port_lbk->lbk_mode)
        {
            port_assign.fwd_gport       = sys_dst_gport;
        }

        CTC_ERROR_RETURN(_sys_usw_internal_port_allocate(lchip, &port_assign, NULL));

        sys_internal_lport = port_assign.inter_port;

        sys_internal_gport = CTC_MAP_LPORT_TO_GPORT(gchip, sys_internal_lport);

        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "source gport:0x%04X, dest gport:0x%04X, internal lport = %u!\n",\
                                               sys_src_gport, sys_dst_gport, sys_internal_lport);

        /* map network port to internal port */
        drv_internal_lport = SYS_MAP_SYS_LPORT_TO_DRV_LPORT(sys_internal_lport);

        if (CTC_PORT_LBK_MODE_EFM == p_port_lbk->lbk_mode)
        {
            /*efm loopback*/
            uint32 chan = 0;
            dmps_port_info.gport = sys_src_gport;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan));
            RET_PROCESS_WITH_ERROR(sys_usw_add_port_to_channel(lchip, drv_internal_lport, chan, 0));
	        RET_PROCESS_WITH_ERROR(sys_usw_add_port_to_channel(lchip, drv_src_lport, MCHIP_CAP(SYS_CAP_CHANID_DROP), 0));
            /*get reflect nexthop*/
            RET_PROCESS_WITH_ERROR(sys_usw_nh_get_reflective_dsfwd_offset(lchip, &dsfwd_offset));
        }
        else if(CTC_PORT_LBK_MODE_CC == p_port_lbk->lbk_mode)
        {
            /*
            if (src_gport == dst_gport)
            {
                RET_PROCESS_WITH_ERROR(sys_usw_add_port_to_channel(lchip, inter_gport, src_lport));
                RET_PROCESS_WITH_ERROR(sys_usw_add_port_to_channel(lchip, src_gport, MCHIP_CAP(SYS_CAP_CHANID_DROP)));
            }
            */

            if (CTC_PORT_LBK_TYPE_SWAP_MAC == p_port_lbk->lbk_type)
            {
                nh_param.type           = CTC_MISC_NH_TYPE_FLEX_EDIT_HDR;
                nh_param.gport          = sys_dst_gport;
                nh_param.dsnh_offset    = 0;

                nh_param.misc_param.l2edit.is_reflective    = 0;
                nh_param.misc_param.l2edit.flag             |= CTC_MISC_NH_FLEX_EDIT_REPLACE_L2_HDR;
                nh_param.misc_param.l2edit.flag             |= CTC_MISC_NH_FLEX_EDIT_SWAP_MACDA;

                sys_usw_nh_add_misc(lchip, &nhid, &nh_param, TRUE);
                CTC_ERROR_RETURN(sys_usw_nh_get_dsfwd_offset(lchip, nhid, &dsfwd_offset, 0, CTC_FEATURE_PORT));

            }
            else if (CTC_PORT_LBK_TYPE_BYPASS == p_port_lbk->lbk_type)
            {
                uint32 bypass_nhid    = 0;
                sys_usw_l2_get_ucast_nh(lchip, sys_dst_gport, CTC_NH_PARAM_BRGUC_SUB_TYPE_BYPASS, &bypass_nhid);

                CTC_ERROR_RETURN(sys_usw_nh_get_dsfwd_offset(lchip, bypass_nhid, &dsfwd_offset, 0, CTC_FEATURE_PORT));

            }
        }

        /*set lbk port property*/
        RET_PROCESS_WITH_ERROR(_sys_usw_port_set_lbk_port_property(lchip, p_port_lbk, sys_internal_lport, dsfwd_offset));
        RET_PROCESS_WITH_ERROR(_sys_usw_port_maping_to_local_phy_port(lchip, sys_src_gport, drv_internal_lport));
        if (CTC_E_NONE != ret)
        {
            if (CTC_PORT_LBK_MODE_EFM == p_port_lbk->lbk_mode)
            {
                /*resverv channel*/
                dmps_port_info.gport = sys_src_gport;
                CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan));
                RET_PROCESS_WITH_ERROR(sys_usw_remove_port_from_channel(lchip, drv_internal_lport, chan));
                RET_PROCESS_WITH_ERROR(sys_usw_remove_port_from_channel(lchip, drv_src_lport, MCHIP_CAP(SYS_CAP_CHANID_DROP)));
                RET_PROCESS_WITH_ERROR(sys_usw_add_port_to_channel(lchip, drv_src_lport, chan, 0));
            }
            else if(CTC_PORT_LBK_MODE_CC == p_port_lbk->lbk_mode)
            { /*release nexthop*/
                if (nhid)
                {
                    sys_usw_nh_remove_misc(lchip, nhid);
                }
            }

            /* Release internal port */
            port_assign.type        = CTC_INTERNAL_PORT_TYPE_FWD;
            port_assign.gchip       = gchip;
            sys_internal_lport = port_assign.inter_port;
            port_assign.inter_port  = sys_internal_lport;
            if (CTC_PORT_LBK_MODE_EFM == p_port_lbk->lbk_mode)
            {
                port_assign.fwd_gport       = sys_src_gport;
            }
            else if(CTC_PORT_LBK_MODE_CC == p_port_lbk->lbk_mode)
            {
                port_assign.fwd_gport       = sys_dst_gport;
            }
            CTC_ERROR_RETURN(_sys_usw_internal_port_release(lchip, &port_assign));

            return ret;
        }

        p_port_lbk->lbk_gport = sys_internal_gport;

        /*save the port*/
        p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].inter_lport = sys_internal_lport;
        p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].lbk_en   = 1;
        p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].nhid     = nhid;
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);
    }
    else
    {
        if (!p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].lbk_en)
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Entry not exist \n");
            return CTC_E_NOT_EXIST;

        }

        p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].lbk_en = 0;
        sys_internal_lport = p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].inter_lport;
        nhid        = p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].nhid;
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);

        drv_internal_lport = SYS_MAP_SYS_LPORT_TO_DRV_LPORT(sys_internal_lport);
        CTC_ERROR_RETURN(_sys_usw_port_maping_to_local_phy_port(lchip, sys_src_gport, drv_src_lport));
        sys_internal_gport = CTC_MAP_LPORT_TO_GPORT(gchip, sys_internal_lport);
        CTC_ERROR_RETURN(_sys_usw_port_set_lbk_port_property(lchip, p_port_lbk, sys_internal_lport, 0));

        /* valid internal port not suppose to be 0 */
        if (sys_internal_lport)
        {
            sys_internal_gport = CTC_MAP_LPORT_TO_GPORT(gchip, sys_internal_lport);

            if (CTC_PORT_LBK_MODE_EFM == p_port_lbk->lbk_mode)
            {
                dmps_port_info.gport = sys_src_gport;
                CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan));
                CTC_ERROR_RETURN(sys_usw_remove_port_from_channel(lchip, drv_internal_lport, chan));
                CTC_ERROR_RETURN(sys_usw_remove_port_from_channel(lchip, drv_internal_lport, MCHIP_CAP(SYS_CAP_CHANID_DROP)));
                CTC_ERROR_RETURN(sys_usw_add_port_to_channel(lchip, drv_src_lport, chan, 0));
            }
            else if(CTC_PORT_LBK_MODE_CC == p_port_lbk->lbk_mode)
            {
                /*
                if (src_gport == dst_gport)
                {
                    CTC_ERROR_RETURN(sys_usw_remove_port_from_channel(lchip, inter_gport, src_lport));
                    CTC_ERROR_RETURN(sys_usw_remove_port_from_channel(lchip, src_gport, MCHIP_CAP(SYS_CAP_CHANID_DROP)));
                    CTC_ERROR_RETURN(sys_usw_add_port_to_channel(lchip, src_gport, src_lport));
                }
                */
                /*release nexthop*/
                if (nhid)
                {
                    sys_usw_nh_remove_misc(lchip, nhid);
                }
            }

            /* Release internal port */
            port_assign.type        = CTC_INTERNAL_PORT_TYPE_FWD;
            port_assign.gchip       = gchip;
            sys_internal_lport = SYS_MAP_DRV_LPORT_TO_SYS_LPORT((SYS_MAP_SYS_LPORT_TO_DRV_LPORT(sys_internal_lport)));
            port_assign.inter_port  = sys_internal_lport;
            if (CTC_PORT_LBK_MODE_EFM == p_port_lbk->lbk_mode)
            {
                port_assign.fwd_gport       = sys_src_gport;
            }
            else if(CTC_PORT_LBK_MODE_CC == p_port_lbk->lbk_mode)
            {
                port_assign.fwd_gport       = sys_dst_gport;
            }
            CTC_ERROR_RETURN(_sys_usw_internal_port_release(lchip, &port_assign));
        }
        p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].inter_lport = 0;
        p_usw_port_master[lchip]->port_prop[CTC_MAP_GPORT_TO_LPORT(sys_src_gport)].nhid     = 0;
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_loopback(uint8 lchip, ctc_port_lbk_param_t* p_port_lbk)
{
    /* debug */
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,"src_gport%d, dst_gport:%d, lbk_enable:%d, lbk_mode:%d\n",p_port_lbk->src_gport,
                            p_port_lbk->dst_gport, p_port_lbk->lbk_enable, p_port_lbk->lbk_mode);

    /* set loopback by lbk_mode */
    if(CTC_PORT_LBK_MODE_TAP != p_port_lbk->lbk_mode)
    {
        CTC_ERROR_RETURN(_sys_usw_port_set_loopback(lchip, p_port_lbk));
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_default_vlan(uint8 lchip, uint32 gport, uint32 value)
{
    uint16  lport = 0;
    uint32  cmd = 0;
    uint32  default_vlan_id = value;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X, default vlan:%d \n", gport, value);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultVlanId_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &default_vlan_id));

    cmd = _sys_usw_port_is_support_glb_port(lchip) ? \
        DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultVlanId_f) : DRV_IOW(DsDestPort_t, DsDestPort_defaultVlanId_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &default_vlan_id));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_mux_type(uint8 lchip, uint16 gport, uint32 value)
{
    uint32 chan_id = 0;
    uint32 cmd  = 0;
    uint8 mux_type = 0;
    uint32 field_val = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    dmps_port_info.gport = gport;

    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
    if (chan_id == SYS_COMMON_USELESS_CHANNEL || !SYS_IS_NETWORK_CHANNEL(chan_id))
    {
        return CTC_E_INVALID_PARAM;
    }

    switch (value)
    {
    case CTC_PORT_MUX_TYPE_NONE:
        mux_type = 0;
        break;
    case CTC_PORT_MUX_TYPE_CLOUD_L2_HDR:
        mux_type = (DRV_IS_DUET2(lchip))?7:8;
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    cmd = DRV_IOW(IpePhyPortMuxCtl_t, IpePhyPortMuxCtl_muxType_f);
    field_val = mux_type;
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &field_val));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_mux_type(uint8 lchip, uint16 gport, uint32* p_value)
{
    uint32 chan_id = 0;
    uint32 cmd  = 0;
    uint32 field_val = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    CTC_PTR_VALID_CHECK(p_value);
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
	if (chan_id == SYS_COMMON_USELESS_CHANNEL || !SYS_IS_NETWORK_CHANNEL(chan_id))
    {
        return CTC_E_INVALID_PARAM;
    }

    cmd = DRV_IOR(IpePhyPortMuxCtl_t, IpePhyPortMuxCtl_muxType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &field_val));
    if (!field_val)
    {
        *p_value = CTC_PORT_MUX_TYPE_NONE;
    }
    else
    {
        if (((field_val == 7) && DRV_IS_DUET2(lchip)) || ((field_val == 8) && !DRV_IS_DUET2(lchip)))
        {
            *p_value = CTC_PORT_MUX_TYPE_CLOUD_L2_HDR;
        }
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_raw_packet_type(uint8 lchip, uint32 gport, uint32 value)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    DsPhyPort_m ds_phy_port;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set gport:0x%04X, packet type:%d \n", gport, value);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    CTC_MAX_VALUE_CHECK(value, CTC_PORT_RAW_PKT_MAX-1);

    sal_memset(&ds_phy_port, 0, sizeof(DsPhyPort_m));

    cmd = DRV_IOR(DsPhyPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port));

    SetDsPhyPort(V, packetTypeValid_f, &ds_phy_port, 1);
    switch (value)
    {
    case CTC_PORT_RAW_PKT_ETHERNET:
        SetDsPhyPort(V, packetType_f, &ds_phy_port, 0);
        break;

    case CTC_PORT_RAW_PKT_IPV4:
        SetDsPhyPort(V, packetType_f, &ds_phy_port, 1);
        break;

    case CTC_PORT_RAW_PKT_IPV6:
        SetDsPhyPort(V, packetType_f, &ds_phy_port, 3);
        break;

    case CTC_PORT_RAW_PKT_NOP:
        SetDsPhyPort(V, packetType_f, &ds_phy_port, 7);
        break;

    case CTC_PORT_RAW_PKT_MPLS:
        SetDsPhyPort(V, packetType_f, &ds_phy_port, 2);
        break;

    default:
        SetDsPhyPort(V, packetTypeValid_f, &ds_phy_port, 0);
        break;
    }

    cmd = DRV_IOW(DsPhyPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_raw_packet_type(uint8 lchip, uint32 gport, uint32* p_value)
{
    uint16  lport = 0;
    uint32  cmd = 0;
    uint32  packet_type_valid = 0;
    uint32  packet_type = 0;
    DsPhyPort_m ds_phy_port;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    /*Sanity check*/
    CTC_PTR_VALID_CHECK(p_value);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    sal_memset(&ds_phy_port, 0, sizeof(DsPhyPort_m));
    cmd = DRV_IOR(DsPhyPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port));

    CTC_ERROR_RETURN(GetDsPhyPort(A, packetTypeValid_f, &ds_phy_port, &packet_type_valid));
    CTC_ERROR_RETURN(GetDsPhyPort(A, packetType_f, &ds_phy_port, &packet_type));

    if (0 == packet_type_valid)
    {
        *p_value = CTC_PORT_RAW_PKT_NONE;
    }
    else
    {
        switch (packet_type)
        {
        case 0:
            *p_value = CTC_PORT_RAW_PKT_ETHERNET;
            break;

        case 1:
            *p_value = CTC_PORT_RAW_PKT_IPV4;
            break;

        case 3:
            *p_value = CTC_PORT_RAW_PKT_IPV6;
            break;

        case 2:
            *p_value = CTC_PORT_RAW_PKT_MPLS;
            break;

        case 7:
            *p_value = CTC_PORT_RAW_PKT_NOP;
            break;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_usw_port_set_port_reflective(uint8 lchip, uint16 lport, uint8 enable)
{
    if(enable)
    {
        CTC_BMP_SET(p_usw_port_master[lchip]->reflect_en, lport);
    }
    else
    {
        CTC_BMP_UNSET(p_usw_port_master[lchip]->reflect_en, lport);
    }

    if(DRV_FROM_TMM(lchip))
    {
        uint32 cmd;
        MetFifoHairPinCheckPort_m check_port;
        DsMetLinkAggregatePort_m agg_port;
        MetFifoHairPinCheckLag_m lag_check_bmp;
        uint32 lag_bmp[16];
        uint8  linkagg_id;

        cmd = DRV_IOR(MetFifoHairPinCheckPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &check_port));
        SetMetFifoHairPinCheckPort(A, pBitmap_f, &check_port, p_usw_port_master[lchip]->reflect_en);
        cmd = DRV_IOW(MetFifoHairPinCheckPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &check_port));

        cmd = DRV_IOR(DsMetLinkAggregatePort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &agg_port));
        if(!GetDsMetLinkAggregatePort(V, linkAggregationEn_f, &agg_port))
        {
            return CTC_E_NONE;
        }

        linkagg_id = GetDsMetLinkAggregatePort(V, linkAggregationId_f, &agg_port);
        cmd = DRV_IOR(MetFifoHairPinCheckLag_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_check_bmp));
        GetMetFifoHairPinCheckLag(A, lagBitmap_f, &lag_check_bmp, lag_bmp);

        if(enable)
        {
            CTC_BMP_SET(lag_bmp, linkagg_id);
        }
        else
        {
            CTC_BMP_UNSET(lag_bmp, linkagg_id);
        }
        SetMetFifoHairPinCheckLag(A, lagBitmap_f, &lag_check_bmp, lag_bmp);
        cmd = DRV_IOW(MetFifoHairPinCheckLag_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &lag_check_bmp));
    }
    return CTC_E_NONE;
}

int32
_sys_usw_port_get_aps_failover_en(uint8 lchip, uint32 gport, uint32* enable)
{
    DsApsChannelMap_m ds_aps_channel_map;
    uint32 channel_id = 0;
    uint32 cmd =0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    /*gport get channel id.*/
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
    if (SYS_COMMON_USELESS_CHANNEL == channel_id || !SYS_IS_NETWORK_CHANNEL(channel_id))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;

    }

    cmd = DRV_IOR(DsApsChannelMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds_aps_channel_map));

    *enable = GetDsApsChannelMap(V, linkChangeEn_f, &ds_aps_channel_map);

    return CTC_E_NONE;
}

int32
_sys_usw_port_get_linkagg_failover_en(uint8 lchip, uint32 gport, uint32* enable)
{
    DsLinkAggregateChannel_m linkagg_channel;
    uint32 channel_id = 0;
    uint32 cmd =0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    /*lport = CTC_MAP_GPORT_TO_LPORT(gport);*/
    if(DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    /*gport get channel id.*/
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
    if (SYS_COMMON_USELESS_CHANNEL == channel_id || !SYS_IS_NETWORK_CHANNEL(channel_id))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;

    }

    /*get ds_aps_channel_map.link_change_en for scio scan down notify aps model.*/
    cmd = DRV_IOR(DsLinkAggregateChannel_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &linkagg_channel));

    *enable =  GetDsLinkAggregateChannel(V, linkChangeEn_f, &linkagg_channel);

    return CTC_E_NONE;
}

int32
_sys_usw_port_set_linkagg_failover_en(uint8 lchip, uint32 gport, bool enable)
{
    uint32 channel_id = 0;
    uint32 cmd =0;
    DsLinkAggregateChannel_m linkagg_channel;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    sal_memset(&linkagg_channel, 0, sizeof(DsLinkAggregateChannel_m));
    if(DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    /*lport = CTC_MAP_GPORT_TO_LPORT(gport);*/

    /*gport get channel id.*/
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
    if (SYS_COMMON_USELESS_CHANNEL == channel_id || !SYS_IS_NETWORK_CHANNEL(channel_id))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;

    }

    /*set linkagg_channel.link_change_en  for scio scan down notify linkagg model.*/
    cmd = DRV_IOR(DsLinkAggregateChannel_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &linkagg_channel));
    SetDsLinkAggregateChannel(V, groupEn_f, &linkagg_channel, 1);
    SetDsLinkAggregateChannel(V, linkChangeEn_f, &linkagg_channel, enable);
    cmd = DRV_IOW(DsLinkAggregateChannel_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &linkagg_channel));

    return CTC_E_NONE;
}

int32
_sys_usw_port_set_aps_failover_en(uint8 lchip, uint32 gport, bool enable)
{
    DsApsChannelMap_m ds_aps_channel_map;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    uint32 channel_id = 0;
    uint32 cmd =0;

    uint16 lport = 0;

    /*lport = CTC_MAP_GPORT_TO_LPORT(gport);*/

     /*linkagg port check return.*/
    if(CTC_IS_LINKAGG_PORT(gport))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " [Aps] Aps only support hw-based aps for phyport \n");
        return CTC_E_NOT_SUPPORT;

    }

    /*gport get channel id.*/
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
    if (SYS_COMMON_USELESS_CHANNEL == channel_id || !SYS_IS_NETWORK_CHANNEL(channel_id))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;

    }

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    /*Set ds_aps_channel_map.link_change_en for scio scan down notify aps model.*/
    cmd = DRV_IOR(DsApsChannelMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds_aps_channel_map));
    SetDsApsChannelMap(V, linkChangeEn_f, &ds_aps_channel_map, enable);
    SetDsApsChannelMap(V, localPhyPort_f, &ds_aps_channel_map, lport);
    cmd = DRV_IOW(DsApsChannelMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds_aps_channel_map));


    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_src_guarantee_en(uint8 lchip, uint32 channel_id, bool enable)
{
    uint32 cmd             = 0;
    uint32 srcGuaranteeEn[CTC_CONST32] = {0};
    uint32 chan_tmp = SYS_USW_CHANNEL_ENCODE(channel_id); /* for TMG, chan bit7 is dpid, bit6 is not use */
    QWriteGuaranteeCtl_m  guarantee_ctl;
    IpeHeaderAdjustChannelPortMap_m port_map;
    uint8 step = 0;

    if (!DRV_FROM_AT(lchip))
    {
        cmd = DRV_IOR(QWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &guarantee_ctl));
        GetQWriteGuaranteeCtl(A,srcGuaranteeEn_f,&guarantee_ctl,srcGuaranteeEn);
        enable? CTC_BIT_SET(srcGuaranteeEn[chan_tmp / CTC_CONST32], chan_tmp % CTC_CONST32):
            CTC_BIT_UNSET(srcGuaranteeEn[chan_tmp / CTC_CONST32], chan_tmp % CTC_CONST32);
        SetQWriteGuaranteeCtl(A, srcGuaranteeEn_f, &guarantee_ctl, srcGuaranteeEn);
        cmd = DRV_IOW(QWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &guarantee_ctl));
    }
    else
    {
        uint8  index     = 0;
        uint8  dp_id     = 0;
        uint8  pp_id     = 0;
        uint16 sub_chan  = 0;

        /* set srcGuaranteeEn IpeHeaderAdjustChannelPortMap(per pp) */
        CTC_ERROR_RETURN(sys_usw_port_api_get_sub_chan_by_chan(lchip, 0, channel_id, &sub_chan, &pp_id, &dp_id));
        index  = (dp_id << 5) | (sub_chan);
        cmd = DRV_IOR(IpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, (index & 0x1F), DRV_CMD_PP_EN(cmd), &port_map));
        step = IpeHeaderAdjustChannelPortMap_g_1_srcGuaranteeEn_f - IpeHeaderAdjustChannelPortMap_g_0_srcGuaranteeEn_f;
        SetIpeHeaderAdjustChannelPortMap(V, g_0_srcGuaranteeEn_f + step * ((index>>5)&0x3), &port_map, enable? 1: 0);
        cmd = DRV_IOW(IpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, (index & 0x1F), DRV_CMD_PP_EN(cmd), &port_map));
    }

    return CTC_E_NONE;
}


STATIC int32
_sys_usw_port_set_xpipe_type(uint8 lchip, uint32 gport, uint32 xpipe_type)
{
    uint16 lport           = 0;
    uint32 emac_channel = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    dmps_port_info.gport = gport;
    /* for TM if pmac_channel == CTC_MAX_UINT8_VALUE lport can't enable xpipe */
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, (void *)&emac_channel));
    switch(xpipe_type)
    {
    case CTC_PORT_XPIPE_TYPE_4:
        CTC_ERROR_RETURN(_sys_usw_port_set_src_guarantee_en(lchip, emac_channel, DRV_IS_TSINGMA(lchip)? FALSE:TRUE));
        break;
    case CTC_PORT_XPIPE_TYPE_5:
        CTC_ERROR_RETURN(_sys_usw_port_set_src_guarantee_en(lchip, emac_channel, DRV_IS_TSINGMA(lchip)? TRUE:FALSE));
        break;
    default:
        break;
    }
    p_usw_port_master[lchip]->port_prop[lport].xpipe_type = xpipe_type;
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);

    return CTC_E_NONE;
}

int32
_sys_usw_port_get_aps_select_grp_id(uint8 lchip, uint32 gport, uint32* grp_id)
{
    uint32 cmd = 0;
    uint32 value = 0;

    uint16 lport = 0;
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_apsSelectValid_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
    if (0 == value)
    {
        *grp_id = 0xFFFFFFFF;
    }
    else
    {
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_apsSelectGroupId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, grp_id));
    }

    return CTC_E_NONE;
}

int32
_sys_usw_port_get_wlan_port_type(uint8 lchip, uint32 gport, uint32* p_value)
{
    uint16 lport     = 0;
    uint16 tmp_lport = 0;
    uint32 cmd       = 0;
    uint32 field = 0;
    if (DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    *p_value = CTC_PORT_WLAN_PORT_TYPE_NONE;
    cmd = DRV_IOR(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+lport);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
    tmp_lport = field;
    if (0 != tmp_lport)
    {
        *p_value = CTC_PORT_WLAN_PORT_TYPE_DECAP_WITHOUT_DECRYPT;
        cmd = DRV_IOR(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+tmp_lport+1);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
        if (field == tmp_lport)
        {
            *p_value = CTC_PORT_WLAN_PORT_TYPE_DECAP_WITH_DECRYPT;
        }
    }

    return CTC_E_NONE;
}

int32
_sys_usw_port_set_wlan_port_type(uint8 lchip, uint32 gport, uint32 value)
{
    uint16 lport     = 0;
    uint32 cmd       = 0;
    uint32 field = 0;
    uint16 inter_lport = 0;
    uint8 gchip_id = 0;
    uint32 excp2_en = 0;
    uint32 sub_index = 0;
    uint32 wlan_type = 0;
    DsPhyPortExt_m phy_port_ext;
    DsSrcPort_m src_port;
    ctc_internal_port_assign_para_t port_assign;
    if (DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    CTC_ERROR_RETURN(_sys_usw_port_get_wlan_port_type(lchip, gport, &wlan_type));
    if ((wlan_type != CTC_PORT_WLAN_PORT_TYPE_NONE) && (value != CTC_PORT_WLAN_PORT_TYPE_NONE))
    {
        return CTC_E_IN_USE;
    }
    sal_memset(&port_assign, 0, sizeof(ctc_internal_port_assign_para_t));

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip_id));

    cmd = DRV_IOR(IpeBpduEscapeCtl_t, IpeBpduEscapeCtl_eapolExceptionSubIndex_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &sub_index));
    switch (value)
    {
        case CTC_PORT_WLAN_PORT_TYPE_DECAP_WITH_DECRYPT:
            port_assign.type = CTC_INTERNAL_PORT_TYPE_WLAN;
            port_assign.gchip = gchip_id;
            port_assign.fwd_gport = gport;
            CTC_ERROR_RETURN(_sys_usw_internal_port_allocate(lchip, &port_assign, NULL));
            inter_lport = port_assign.inter_port;
            field = inter_lport;
            cmd = DRV_IOW(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+lport);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
            cmd = DRV_IOW(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+inter_lport+1);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));

            cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));
            field = 1;
            SetDsPhyPortExt(V, capwapHashEn1_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, capwapHashEn2_f, &phy_port_ext, field);
            field = 0x1d;
            SetDsPhyPortExt(V, userIdPortHash1Type_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdPortHash2Type_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdTcam2En_f, &phy_port_ext, field);
            field = 3;
            SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdTcam2Type_f, &phy_port_ext, field);
            field = 0;
            SetDsPhyPortExt(V, tcam1IsSclFlow_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2IsSclFlow_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam1IsUserId_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2IsUserId_f, &phy_port_ext, field);
            cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));

            sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
            cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport+1, cmd, &phy_port_ext));
            field = 1;
            SetDsPhyPortExt(V, capwapHashEn1_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, capwapHashEn2_f, &phy_port_ext, field);
            field = 0x1d;
            SetDsPhyPortExt(V, userIdPortHash1Type_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdPortHash2Type_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdTcam2En_f, &phy_port_ext, field);
            field = 3;
            SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdTcam2Type_f, &phy_port_ext, field);
            field = 0;
            SetDsPhyPortExt(V, tcam1IsSclFlow_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2IsSclFlow_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam1IsUserId_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2IsUserId_f, &phy_port_ext, field);
            cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport+1, cmd, &phy_port_ext));

            sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
            cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport, cmd, &phy_port_ext));

            excp2_en = GetDsPhyPortExt(V, exception2En_f, &phy_port_ext);
            CTC_SET_FLAG(excp2_en, (1 << sub_index));
            SetDsPhyPortExt(V, exception2En_f, &phy_port_ext, excp2_en);

            field = 1;
            SetDsPhyPortExt(V, tcamUseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam1UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam3UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam4UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userId1UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userId2UseLogicPort_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
            field = 3;
            SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
            field = 0;
            SetDsPhyPortExt(V, tcam1IsSclFlow_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, tcam1IsUserId_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, userIdTcam2En_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2IsUserId_f, &phy_port_ext, field);
            field = 0;
            SetDsPhyPortExt(V, userIdTcam2Type_f, &phy_port_ext, field);
            field = 0;
            SetDsPhyPortExt(V, useDefaultLogicSrcPort_f, &phy_port_ext, field);
            cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport, cmd, &phy_port_ext));

            sal_memset(&src_port, 0, sizeof(src_port));
            cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport+1, cmd, &src_port));
            SetDsSrcPort(V, interfaceId_f, &src_port, MCHIP_CAP(SYS_CAP_L3IF_RSV_L3IF_ID));
            SetDsSrcPort(V, routedPort_f, &src_port, 1);
            SetDsSrcPort(V, addDefaultVlanDisable_f, &src_port, 1);
            cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport+1, cmd, &src_port));

            p_usw_port_master[lchip]->network_port[inter_lport] = lport;
            p_usw_port_master[lchip]->network_port[inter_lport+1] = lport;
            break;

        case CTC_PORT_WLAN_PORT_TYPE_DECAP_WITHOUT_DECRYPT:
            port_assign.type = CTC_INTERNAL_PORT_TYPE_FWD;
            port_assign.gchip = gchip_id;
            port_assign.fwd_gport = gport;
            CTC_ERROR_RETURN(_sys_usw_internal_port_allocate(lchip, &port_assign, NULL));
            inter_lport = port_assign.inter_port;
            field = inter_lport;
            cmd = DRV_IOW(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+lport);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));

            cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));
            field = 1;
            SetDsPhyPortExt(V, capwapHashEn1_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, capwapHashEn2_f, &phy_port_ext, field);
            field = 0x1d;
            SetDsPhyPortExt(V, userIdPortHash1Type_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdPortHash2Type_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdTcam2En_f, &phy_port_ext, field);
            field = 3;
            SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userIdTcam2Type_f, &phy_port_ext, field);
            field = 0;
            SetDsPhyPortExt(V, tcam1IsSclFlow_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2IsSclFlow_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam1IsUserId_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2IsUserId_f, &phy_port_ext, field);
            cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));

            sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
            cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport, cmd, &phy_port_ext));

            excp2_en = GetDsPhyPortExt(V, exception2En_f, &phy_port_ext);
            CTC_SET_FLAG(excp2_en, (1 << sub_index));
            SetDsPhyPortExt(V, exception2En_f, &phy_port_ext, excp2_en);

            field = 1;
            SetDsPhyPortExt(V, tcamUseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam1UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam3UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam4UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userId1UseLogicPort_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, userId2UseLogicPort_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
            field = 3;
            SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
            field = 0;
            SetDsPhyPortExt(V, tcam1IsSclFlow_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, tcam1IsUserId_f, &phy_port_ext, field);
            field = 1;
            SetDsPhyPortExt(V, userIdTcam2En_f, &phy_port_ext, field);
            SetDsPhyPortExt(V, tcam2IsUserId_f, &phy_port_ext, field);
            field = (!DRV_IS_DUET2(lchip)) ? 3 : 0;
            SetDsPhyPortExt(V, userIdTcam2Type_f, &phy_port_ext, field);
            field = 0;
            SetDsPhyPortExt(V, useDefaultLogicSrcPort_f, &phy_port_ext, field);
            cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport, cmd, &phy_port_ext));

            p_usw_port_master[lchip]->network_port[inter_lport] = lport;

            break;

        case CTC_PORT_WLAN_PORT_TYPE_NONE:
            port_assign.gchip = gchip_id;
            port_assign.fwd_gport = gport;
            cmd = DRV_IOR(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+lport);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
            inter_lport = field;
            if (0 != inter_lport)
            {
                port_assign.type = CTC_INTERNAL_PORT_TYPE_FWD;
                port_assign.inter_port = inter_lport;
                cmd = DRV_IOR(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+inter_lport+1);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
                if (field == inter_lport)
                {
                    port_assign.type = CTC_INTERNAL_PORT_TYPE_WLAN;
                    field = 0;
                    cmd = DRV_IOW(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+lport);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
                    cmd = DRV_IOW(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+inter_lport+1);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));

                    sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
                    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));
                    field = 0;
                    SetDsPhyPortExt(V, capwapHashEn1_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, capwapHashEn2_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdPortHash1Type_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdPortHash2Type_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam2En_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam2Type_f, &phy_port_ext, field);
                    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));

                    sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
                    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport+1, cmd, &phy_port_ext));
                    field = 0;
                    SetDsPhyPortExt(V, capwapHashEn1_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, capwapHashEn2_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdPortHash1Type_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdPortHash2Type_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam2En_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam2Type_f, &phy_port_ext, field);
                    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport+1, cmd, &phy_port_ext));

                    sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
                    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport, cmd, &phy_port_ext));

                    excp2_en = GetDsPhyPortExt(V, exception2En_f, &phy_port_ext);
                    CTC_UNSET_FLAG(excp2_en, (1 << sub_index));
                    SetDsPhyPortExt(V, exception2En_f, &phy_port_ext, excp2_en);

                    field = 0;
                    SetDsPhyPortExt(V, tcamUseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam1UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam2UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam3UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam4UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userId1UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userId2UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam1IsSclFlow_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam1IsUserId_f, &phy_port_ext, field);
                    field = 1;
                    SetDsPhyPortExt(V, useDefaultLogicSrcPort_f, &phy_port_ext, field);
                    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport, cmd, &phy_port_ext));

                    sal_memset(&src_port, 0, sizeof(src_port));
                    cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport+1, cmd, &src_port));
                    SetDsSrcPort(V, interfaceId_f, &src_port, 0);
                    SetDsSrcPort(V, routedPort_f, &src_port, 0);
                    SetDsSrcPort(V, addDefaultVlanDisable_f, &src_port, 0);
                    cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport+1, cmd, &src_port));

                    p_usw_port_master[lchip]->network_port[inter_lport] = SYS_INVALID_LOCAL_PHY_PORT;
                    p_usw_port_master[lchip]->network_port[inter_lport+1] = SYS_INVALID_LOCAL_PHY_PORT;
                }
                else
                {
                    field = 0;
                    cmd = DRV_IOW(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+lport);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));

                    sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
                    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));
                    field = 0;
                    SetDsPhyPortExt(V, capwapHashEn1_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, capwapHashEn2_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdPortHash1Type_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdPortHash2Type_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam2En_f, &phy_port_ext, field);
                    field = 0;
                    SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam2Type_f, &phy_port_ext, field);
                    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));

                    sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
                    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport, cmd, &phy_port_ext));
                    field = 0;
                    SetDsPhyPortExt(V, tcamUseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam1UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam2UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam3UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam4UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userId1UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userId2UseLogicPort_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam1En_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, userIdTcam1Type_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam1IsSclFlow_f, &phy_port_ext, field);
                    SetDsPhyPortExt(V, tcam1IsUserId_f, &phy_port_ext, field);

                    excp2_en = GetDsPhyPortExt(V, exception2En_f, &phy_port_ext);
                    CTC_UNSET_FLAG(excp2_en, (1 << sub_index));
                    SetDsPhyPortExt(V, exception2En_f, &phy_port_ext, excp2_en);

                    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, inter_lport, cmd, &phy_port_ext));

                    p_usw_port_master[lchip]->network_port[inter_lport] = SYS_INVALID_LOCAL_PHY_PORT;
                }
                CTC_ERROR_RETURN(_sys_usw_internal_port_release (lchip, &port_assign));
            }
            break;
        default:
            return CTC_E_INVALID_PARAM;
            break;
    }
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);
    return CTC_E_NONE;
}

int32
_sys_usw_port_set_wlan_port_route(uint8 lchip, uint32 gport, uint32 value)
{
    uint16 lport     = 0;
    uint16 tmp_lport     = 0;
    uint32 cmd       = 0;
    uint32 field = 0;
    DsSrcPort_m src_port;
    DsPhyPortExt_m phy_port_ext;
    DsPhyPort_m phy_port;

    if (DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOR(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+lport);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
    tmp_lport = field;
    if (0 == tmp_lport)
    {
        return CTC_E_INVALID_PARAM;
    }

    if (value)
    {
        sal_memset(&src_port, 0, sizeof(src_port));
        cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &src_port));
        SetDsSrcPort(V, interfaceId_f, &src_port, MCHIP_CAP(SYS_CAP_L3IF_RSV_L3IF_ID));
        SetDsSrcPort(V, routedPort_f, &src_port, 1);
        SetDsSrcPort(V, addDefaultVlanDisable_f, &src_port, 1);
        cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &src_port));

        sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
        cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &phy_port_ext));
        SetDsPhyPortExt(V, defaultVlanId_f, &phy_port_ext, 0);
        cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &phy_port_ext));

        sal_memset(&phy_port, 0, sizeof(phy_port));
        SetDsPhyPort(V, fwdHashGenDis_f, &phy_port, 1);
        cmd = DRV_IOW(DsPhyPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &phy_port));
    }
    else
    {
        sal_memset(&src_port, 0, sizeof(src_port));
        cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &src_port));
        SetDsSrcPort(V, interfaceId_f, &src_port, 0);
        SetDsSrcPort(V, routedPort_f, &src_port, 0);
        SetDsSrcPort(V, addDefaultVlanDisable_f, &src_port, 0);
        cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &src_port));

        sal_memset(&phy_port_ext, 0, sizeof(phy_port_ext));
        cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &phy_port_ext));
        SetDsPhyPortExt(V, defaultVlanId_f, &phy_port_ext, 1);
        cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &phy_port_ext));

        sal_memset(&phy_port, 0, sizeof(phy_port));
        SetDsPhyPort(V, fwdHashGenDis_f, &phy_port, 0);
        cmd = DRV_IOW(DsPhyPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &phy_port));
    }

    return CTC_E_NONE;
}

int32
_sys_usw_port_get_wlan_port_route(uint8 lchip, uint32 gport, uint32* p_value)
{
    uint16 lport     = 0;
    uint16 tmp_lport     = 0;
    uint16 l3if_id     = 0;
    uint32 cmd       = 0;
    uint32 field = 0;
    DsSrcPort_m src_port;

    if (DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOR(IpeE2iLoopCtl_t, IpeE2iLoopCtl_portArray_0_loopbackPort_f+lport);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
    tmp_lport = field;
    *p_value = 0;
    sal_memset(&src_port, 0, sizeof(src_port));
    cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, tmp_lport, cmd, &src_port));
    l3if_id =  GetDsSrcPort(V, interfaceId_f, &src_port);
    if (MCHIP_CAP(SYS_CAP_L3IF_RSV_L3IF_ID) == l3if_id)
    {
        *p_value = 1;
    }

    return CTC_E_NONE;
}
/*MUST return none when not support global port property*/
STATIC int32
_sys_usw_port_set_global_property(uint8 lchip, uint32 gport, uint32 port_prop, uint32 value)
{
    int32   ret = CTC_E_NONE;
    uint32  cmd = 0;
    uint16  index = 0;
    uint32  temp_value = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set global port property, gport:0x%04X, property:%d, value:%d\n", \
                     gport, port_prop, value);

    if(!_sys_usw_port_is_support_glb_port(lchip) || !p_usw_port_master[lchip]->rchip_gport_idx_cb)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "the callback function for mapping gport to global dest index is not registered!\n");
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " API or some feature is not supported \n");
        return CTC_E_INVALID_PORT;
    }

    CTC_ERROR_RETURN(p_usw_port_master[lchip]->rchip_gport_idx_cb(lchip, gport, &index));

    temp_value = value;
    switch (port_prop)
    {
        case CTC_PORT_PROP_BRIDGE_EN:
            temp_value = value ? 1 : 0;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_bridgeEn_f);
            break;
        case CTC_PORT_DIR_PROP_QOS_COS_DOMAIN:
            CTC_MAX_VALUE_CHECK(value, 7);
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_cosPhbPtr_f);
            break;
        case CTC_PORT_PROP_VLAN_DOMAIN:
        case CTC_PORT_DIR_PROP_VLAN_DOMAIN:
            CTC_MAX_VALUE_CHECK(value, CTC_DOT1Q_TYPE_BOTH);
            temp_value = (CTC_DOT1Q_TYPE_CVLAN == value) ? 1 : 0;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_cvlanSpace_f);
            break;
        case CTC_PORT_PROP_DEFAULT_DEI:
            CTC_MAX_VALUE_CHECK(value, 1);
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultDei_f);
            break;
        case CTC_PORT_PROP_DEFAULT_DSCP:
            if (value > CTC_MAX_QOS_DSCP_VALUE)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultDscp_f);
            break;
        case CTC_PORT_PROP_REPLACE_PCP_DEI:
            temp_value = !!value;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_replacePortPcp_f);
            break;
        case CTC_PORT_PROP_DEFAULT_PCP:
            CTC_MAX_VALUE_CHECK(value, 7);
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultPcp_f);
            break;
        case CTC_PORT_PROP_DEFAULT_VLAN:
            CTC_VLAN_RANGE_CHECK(value);
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultVlanId_f);
            break;
        case CTC_PORT_PROP_DOT1Q_TYPE:
            CTC_MAX_VALUE_CHECK(temp_value, CTC_DOT1Q_TYPE_BOTH);
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dot1QEn_f);
            break;
        case CTC_PORT_DIR_PROP_QOS_DOMAIN:
            CTC_MAX_VALUE_CHECK(temp_value, 7);
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_cosPhbPtr_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value));
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dscpPhbPtr_f);
            break;
        case CTC_PORT_DIR_PROP_QOS_DSCP_DOMAIN:
            CTC_MAX_VALUE_CHECK(value, 15);
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dscpPhbPtr_f);
            break;
        case CTC_PORT_PROP_DSCP_SELECT_MODE:
            CTC_MAX_VALUE_CHECK(value, MAX_CTC_DSCP_SELECT_MODE - 1);
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dscpRemarkMode_f);
            break;

        case CTC_PORT_PROP_PRIORITY_TAG_EN:
            temp_value = !!value;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_priorityTagEn_f);
            break;

        case CTC_PORT_PROP_REPLACE_CTAG_COS:
            temp_value = !!value;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_replaceCtagCos_f);
            break;

        case CTC_PORT_PROP_REPLACE_DSCP_EN:
            temp_value = (value) ? 2 : 0;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dscpRemarkMode_f);
            break;
        case CTC_PORT_PROP_REPLACE_STAG_COS:
            temp_value = !!value;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_replaceStagCos_f);
            break;

        case CTC_PORT_PROP_REPLACE_STAG_TPID:
            temp_value = !!value;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_replaceStagTpid_f);
            break;

        case CTC_PORT_DIR_PROP_STAG_TPID_INDEX:
            if (value > 3 && (0xff != value))
            {
                return CTC_E_INVALID_PARAM;
            }
            temp_value = (0xff == value) ? 0 : 1;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_svlanTpidValid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value));
            temp_value = (0xff == value) ? 0 : value;
            cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_svlanTpidIndex_f);
            break;

        case CTC_PORT_PROP_UNTAG_PVID_TYPE:
            switch(value)
            {
                case CTC_PORT_UNTAG_PVID_TYPE_NONE:
                    temp_value = 0;
                    cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultVlanId_f);
                    ret = DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value);
                    break;

                case CTC_PORT_UNTAG_PVID_TYPE_SVLAN:

                    temp_value = 1;
                    cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultVlanId_f);
                    ret = DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value);
                    temp_value = 1;
                    cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultSvlan_f);
                    ret = ret ? ret : DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value);
                    break;

                case CTC_PORT_UNTAG_PVID_TYPE_CVLAN:

                    temp_value = 1;
                    cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultVlanId_f);
                    ret = DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value);
                    temp_value = 0;
                    cmd = DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultSvlan_f);
                    ret = ret ? ret : DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value);
                    break;

                default:
                    return CTC_E_INVALID_PARAM;
                    break;
            }

            return ret;

        default:
            return CTC_E_NOT_SUPPORT;
    }

    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_global_property(uint8 lchip, uint32 gport, uint32 port_prop, uint32* p_value)
{
    uint32 cmd = 0;
    uint16 index = 0;
    uint32 temp_value = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get global port property, gport:0x%04X, property:%d!\n", gport, port_prop);

    if(!_sys_usw_port_is_support_glb_port(lchip) || !p_usw_port_master[lchip]->rchip_gport_idx_cb)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "the callback function for mapping gport to global dest index is not registered!\n");
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " API or some feature is not supported \n");
        return CTC_E_NOT_SUPPORT;

    }

    CTC_ERROR_RETURN(p_usw_port_master[lchip]->rchip_gport_idx_cb(lchip, gport, &index));

    switch (port_prop)
    {
        case CTC_PORT_PROP_BRIDGE_EN:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_bridgeEn_f);
            break;
        case CTC_PORT_DIR_PROP_QOS_COS_DOMAIN:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_cosPhbPtr_f);
            break;
        case CTC_PORT_DIR_PROP_QOS_DOMAIN:
            {
                uint32 value1 = 0;
                uint32 value2 = 0;

                cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_cosPhbPtr_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value1));
                cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dscpPhbPtr_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value2));
                if(value1 == value2)
                {
                    *p_value = value1;
                }
                else
                {
                    *p_value = 0;
                }
                cmd = 0 ;
                break;
            }
        case CTC_PORT_DIR_PROP_QOS_DSCP_DOMAIN:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dscpPhbPtr_f);
            break;
        case CTC_PORT_PROP_VLAN_DOMAIN:
        case CTC_PORT_DIR_PROP_VLAN_DOMAIN:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_cvlanSpace_f);
            break;
        case CTC_PORT_PROP_DEFAULT_DEI:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_defaultDei_f);
            break;
        case CTC_PORT_PROP_DEFAULT_DSCP:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_defaultDscp_f);
            break;
        case CTC_PORT_PROP_REPLACE_DSCP_EN:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dscpRemarkMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value));
            if(temp_value == 2)
            {
                *p_value = 1;
            }
            else
            {
                *p_value = 0;
            }
            cmd = 0;
            break;
        case CTC_PORT_PROP_REPLACE_PCP_DEI:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_replacePortPcp_f);
            break;
        case CTC_PORT_PROP_DEFAULT_PCP:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_defaultPcp_f);
            break;
        case CTC_PORT_PROP_DEFAULT_VLAN:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_defaultVlanId_f);
            break;
        case CTC_PORT_PROP_DOT1Q_TYPE:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dot1QEn_f);
            break;

        case CTC_PORT_PROP_DSCP_SELECT_MODE:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dscpRemarkMode_f);
            break;

        case CTC_PORT_PROP_PRIORITY_TAG_EN:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_priorityTagEn_f);
            break;

        case CTC_PORT_PROP_REPLACE_CTAG_COS:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_replaceCtagCos_f);
            break;


        case CTC_PORT_PROP_REPLACE_STAG_COS:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_replaceStagCos_f);
            break;

        case CTC_PORT_PROP_REPLACE_STAG_TPID:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_replaceStagTpid_f);
            break;

        case CTC_PORT_DIR_PROP_STAG_TPID_INDEX:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_svlanTpidIndex_f);
            break;

        case CTC_PORT_PROP_UNTAG_PVID_TYPE:
            cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_untagDefaultVlanId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value));
            if (!temp_value) /* none */
            {
                *p_value = CTC_PORT_UNTAG_PVID_TYPE_NONE;
            }
            else /* s or c */
            {
                cmd = DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_untagDefaultSvlan_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &temp_value));

                if (temp_value) /* s */
                {
                    *p_value = CTC_PORT_UNTAG_PVID_TYPE_SVLAN;
                }
                else
                {
                    *p_value = CTC_PORT_UNTAG_PVID_TYPE_CVLAN;
                }
            }
            return CTC_E_NONE;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    if(cmd)
    {
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, p_value));
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_dmps_channel(uint8 lchip, uint32 gport, uint8 dmps_port_prop, uint32 mode)
{
    uint8  index     = 0;
    uint8  mac_num   = 0;
    uint8  chan_num  = 0;
    uint32 chan_id[SYS_USW_MAX_CHANEL_NUM_PER_PORT] = {0};    /* 0: low prio channel(origin channel), 1: middle prio channel 2: high prio channel */
    uint32 mac_id[SYS_USW_MAX_CHANEL_NUM_PER_PORT]  = {0};    /* 0: low prio mac, 1: middle prio mac 2: high prio mac(origin mac) */

    CTC_ERROR_RETURN(sys_usw_port_api_get_mac(lchip, 0, gport, mac_id, &mac_num));
    CTC_ERROR_RETURN(sys_usw_port_api_get_channel(lchip, 0, gport, chan_id, &chan_num));

    for (index = 0; index < chan_num; index++ )
    {
        CTC_ERROR_RETURN(sys_usw_port_api_check_datapath_credit_clear(lchip, mac_id[index], chan_id[index]));
    }

    CTC_ERROR_RETURN(sys_usw_dmps_set_port_property(lchip, gport, dmps_port_prop, &mode));

    return CTC_E_NONE;
}

int32
sys_usw_port_get_channel(uint8 lchip, uint8 rx, uint32 gport, uint32* chan, uint8* chan_num)
{
    uint8  idx   = 0; 
    uint32 chan_id[SYS_USW_MAX_CHANEL_NUM_PER_PORT] = {0};

    /* chan[0] is origin chan whether enable xpipe or not */
    *chan_num = 0;

    if (DRV_FROM_AT(lchip))
    {
        sys_usw_dmps_port_info_t port_info = {0};
        port_info.gport = gport;
        port_info.rx = rx;
        if(CTC_IS_MCHAN_PORT(gport))
        {
            CTC_MAX_VALUE_CHECK(CTC_MAP_GPORT_TO_MCHAN_IDX(gport), SYS_USW_MAX_CHANEL_NUM_PER_PORT - 1);
            port_info.index = CTC_MAP_GPORT_TO_MCHAN_IDX(gport);
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id[0]));
            if (SYS_COMMON_USELESS_CHANNEL == chan_id[idx])
            {
                return CTC_E_INVALID_PORT;
            }
            *chan_num = 1;
        }
        else
        {
            for (idx = 0; idx < SYS_USW_MAX_CHANEL_NUM_PER_PORT; idx++)
            {
                port_info.index = idx;
                CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id[idx]));
                if (SYS_COMMON_USELESS_CHANNEL == chan_id[idx])
                {
                    break;
                }
                *chan_num += 1;
            }
        }
    }
    else
    {
        sys_usw_dmps_port_info_t dmps_port_info = {0};
        dmps_port_info.gport = gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id[0]));
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_GET_PMAC_CHAN_ID, &chan_id[1]));
        *chan_num = (SYS_COMMON_USELESS_CHANNEL != chan_id[1])? 2: 1;
    }

    for (idx = 0; idx < *chan_num; idx++)
    {
        chan[idx] = chan_id[idx];
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_get_mac(uint8 lchip, uint8 rx, uint32 gport, uint32* mac, uint8* mac_num)
{
    uint8  idx     = 0; 
    uint8  reverse = 0;
    uint32 mac_tmp = 0;
    uint32 mac_id[SYS_USW_MAX_CHANEL_NUM_PER_PORT] = {0};
    sys_usw_dmps_port_info_t port_info = {0};

    /* mac[mac_num] is origin mac */
    port_info.gport = gport;
    *mac_num = 0;

    if (DRV_FROM_AT(lchip))
    {
        port_info.rx = rx;
        for (idx = 0; idx < SYS_USW_MAX_CHANEL_NUM_PER_PORT; idx++)
        {
            port_info.index = idx;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &port_info, SYS_PORT_API_DMPS_PROP_GET_PMAC_ID, &mac_id[idx]));
            if(SYS_COMMON_USELESS_MAC == mac_id[idx])
            {
                break;
            }
            *mac_num += 1;
        }
        reverse = (rx && (1 < *mac_num)) ? 1 : 0;
    }
    else
    {
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &port_info, SYS_PORT_API_DMPS_PROP_GET_PMAC_ID, &mac_tmp));

        if(SYS_COMMON_USELESS_MAC != mac_tmp)
        {
            mac_id[0] = mac_tmp;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, &mac_id[1]));
        }
        else
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, &mac_id[0]));
        }

        *mac_num = (SYS_COMMON_USELESS_MAC != mac_tmp)? 2: 1;
    }

    for (idx = 0; idx < *mac_num; idx++)
    {
        mac[idx] = reverse ?  mac_id[*mac_num - 1 - idx] : mac_id[idx];
    }

    return CTC_E_NONE;
}

int32
_sys_usw_port_set_xpipe_channel(uint8 lchip, uint32 lport)
{
    DsQWriteGuarantee_m qwrite_guarantee;
    uint32 port_type = 0;
    uint32 cmd = 0;
    uint32 xpipe_enable = 0;
    uint8 gchip = 0;
    uint32 channel_id = 0;
    uint32 chan_tmp = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
    dmps_port_info.gport = CTC_MAP_LPORT_TO_GPORT(gchip, lport);
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, (void *)&channel_id));
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
    if ((SYS_DMPS_NETWORK_PORT == port_type) || (SYS_DMPS_CPUMAC_NETWORK_PORT == port_type))
    {
        xpipe_enable = p_usw_port_master[lchip]->port_prop[lport].xpipe_type;
    }

    /* only support XPIPE_TYEPE_4 and XPIPE_TYPE_5 config*/
    chan_tmp = SYS_USW_CHANNEL_ENCODE(channel_id);
    if (xpipe_enable)
    {
        if(CTC_PORT_XPIPE_TYPE_4 != xpipe_enable && CTC_PORT_XPIPE_TYPE_5 != xpipe_enable)
        {
            return CTC_E_NOT_SUPPORT;
        }
        CTC_ERROR_RETURN(_sys_usw_port_set_xpipe_type(lchip, dmps_port_info.gport, xpipe_enable));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_usw_port_set_src_guarantee_en(lchip, channel_id, TRUE));
    }

    cmd = DRV_IOR(DsQWriteGuarantee_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, chan_tmp, cmd, &qwrite_guarantee));

    SetDsQWriteGuarantee(V, destGuaranteeChannel_f, &qwrite_guarantee, chan_tmp);
    cmd = DRV_IOW(DsQWriteGuarantee_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, chan_tmp, cmd, &qwrite_guarantee));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_check_xpipe_type(uint8 lchip, uint32 gport, uint16 lport, uint32 value)
{
    uint32 xpipe_en    = 0;
    uint32 old_mode    = 0;
    uint32 fast_pfc    = 0;

    if (DRV_IS_DUET2(lchip) || !MCHIP_SUB_FEATURE_CAP(lchip, SYS_FEATURE_QOS_XIPIP) || CTC_IS_MCHAN_PORT(gport) ||
      ((CTC_PORT_XPIPE_TYPE_1 == value || CTC_PORT_XPIPE_TYPE_3 == value) && DRV_IS_AT(lchip)) ||
      (CTC_PORT_XPIPE_TYPE_2 == value && DRV_IS_TSINGMA(lchip)))
    {
        return CTC_E_NOT_SUPPORT;
    }
    CTC_MAX_VALUE_CHECK(value, (CTC_PORT_XPIPE_TYPE_MAX-1))

    xpipe_en = p_usw_port_master[lchip]->port_prop[lport].xpipe_type;
    if(xpipe_en == value)
    {
        return CTC_E_EXIST;
    }
    if (xpipe_en && value)
    {
        return CTC_E_IN_USE;
    }

    /* need clear fast pfc before cfg */
    if (DRV_FROM_AT(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_port_get_property(lchip, gport, CTC_PORT_PROP_FAST_PFC_EN, &fast_pfc));
        if (fast_pfc && (xpipe_en != value))
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Xpipe can not cfg igs feature on fast-ecn enable\n");
            return CTC_E_INVALID_CONFIG;
        }

        CTC_ERROR_RETURN(sys_usw_port_get_property(lchip, gport, CTC_PORT_PROP_XPIPE_MODE, &old_mode));
        if (value && (CTC_XPIPE_MODE_4 == old_mode || CTC_XPIPE_MODE_5 == old_mode))
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Xpipe not support enable igs feature on CTC_XPIPE_MODE_4 or CTC_XPIPE_MODE_5\n");
            return CTC_E_NOT_SUPPORT;
        }
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_xpipe_enable(uint8 lchip, uint32 gport, uint32 value)
{
    uint16 lport     = 0;

    lport = CTC_MAP_GPORT_TO_LPORT(gport);

    /* modify xpipe src dir priority don't need alloc other resource*/
    if (CTC_PORT_XPIPE_TYPE_4 == value || CTC_PORT_XPIPE_TYPE_5 == value)
    {
        return _sys_usw_port_set_xpipe_type(lchip, gport, value);
    }
    else if (!(DRV_FROM_AT(lchip) && CTC_PORT_XPIPE_TYPE_6 == value))
    {
        /*for TM.MX, only set xpipe en(rx) can alloc and free new channel*/
        CTC_ERROR_RETURN(_sys_usw_port_set_dmps_channel(lchip, gport, SYS_PORT_API_DMPS_PROP_XPIPE_RX, value));
    }
    if (MCHIP_PORT(lchip)->port_set_xpipe_en)
    {
        CTC_ERROR_RETURN(MCHIP_PORT(lchip)->port_set_xpipe_en(lchip, gport, value));
    }

    p_usw_port_master[lchip]->port_prop[lport].xpipe_type = value;
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);

    return CTC_E_NONE;
}

int32
_sys_usw_port_get_xpipe_enable(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32* p_value)
{
    DsQWriteGuarantee_m qwrite_guarantee;
    QWriteGuaranteeCtl_m  guarantee_ctl;
    uint32  srcGuaranteeEn[32] = {0};
    uint32 cmd = 0;
    uint16 lport = 0;
    uint32 channel_id = 0;
    uint32 index = 0;
    uint32  port_type = 0;
    uint32  port_mac_id = 0;
    uint8   gchip = SYS_MAP_CTC_GPORT_TO_GCHIP(gport);
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    if (DRV_IS_DUET2(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    lport = CTC_MAP_GPORT_TO_LPORT(gport);
    if(lport >= MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP))
    {
        return CTC_E_INVALID_PORT;
    }
    if (DRV_IS_TSINGMA(lchip))
    {
        uint16 pmac_channel[24] = {4, 5, 6, 7, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27, 40, 41, 42, 43, 56, 57, 58, 59};
        uint16 emac_channel[24] = {0, 1, 2, 3, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31, 44, 45, 46, 47, 60, 61, 62, 63};
        for (index = 0; index < 24; index ++)
        {
            if (pmac_channel[index] == lport)
            {
                gport = SYS_MAP_DRV_LPORT_TO_CTC_GPORT(gchip, emac_channel[index]);
                break;
            }
        }
    }
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
    if ((SYS_DMPS_NETWORK_PORT != port_type) && (port_type != SYS_DMPS_CPUMAC_NETWORK_PORT))
    {
        *p_value = FALSE;
        return CTC_E_NONE;
    }
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, (void *)&port_mac_id));
    if (DRV_IS_TSINGMA(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_GET_PMAC_CHAN_ID, (void *)&index));
        CTC_BIT_UNSET(srcGuaranteeEn[index / 32], index % 32);
        CTC_BIT_SET(srcGuaranteeEn[channel_id / 32], channel_id % 32);
    }
    else
    {
        uint8   dp_id = 0;
        uint32 emac_id_per_txqm = 0;
        uint8 txqm_id = 0;
        uint32 step = 0;
        uint32 value[2] = {0};
        uint32 port_type = 0;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
        if((SYS_DMPS_NETWORK_PORT != port_type) && (SYS_DMPS_CPUMAC_NETWORK_PORT != port_type))
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Gport %u is not a network port! \n", gport);
            return CTC_E_INVALID_PORT;
        }
        dp_id = (MCHIP_CAP(SYS_CAP_MAX_MAC_NUM) <= port_mac_id) ? ((port_mac_id - MCHIP_CAP(SYS_CAP_MAX_MAC_NUM)) / MCHIP_CAP(SYS_CAP_MAX_MISC_CHANNEL)) : (port_mac_id / MCHIP_CAP(SYS_CAP_MAX_MAC_NUM_PER_DP));
        txqm_id = (port_mac_id / MCHIP_CAP(SYS_CAP_MAX_MAC_NUM_PER_TXQM)) - (dp_id * MCHIP_CAP(SYS_CAP_TXQM_NUM_PER_DP));
        emac_id_per_txqm = port_mac_id % MCHIP_CAP(SYS_CAP_MAX_MAC_NUM_PER_TXQM);
        step = NetRxPortSplitEnCtl_portSplitEn1_f - NetRxPortSplitEnCtl_portSplitEn0_f;
        cmd = DRV_IOR(NetRxPortSplitEnCtl_t, NetRxPortSplitEnCtl_portSplitEn0_f + step*txqm_id);
        DRV_FIELD_IOCTL(lchip, dp_id, cmd, value);
        if (emac_id_per_txqm < 32)
        {
            *p_value = CTC_IS_BIT_SET(value[0], emac_id_per_txqm);
        }
        else
        {
            *p_value = CTC_IS_BIT_SET(value[1], emac_id_per_txqm-32);
        }
    }

    cmd = DRV_IOR(DsQWriteGuarantee_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &qwrite_guarantee));

    SetDsQWriteGuarantee(V, destGuaranteeChannel_f, &qwrite_guarantee, channel_id);
    cmd = DRV_IOW(DsQWriteGuarantee_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &qwrite_guarantee));

    SetQWriteGuaranteeCtl(A, srcGuaranteeEn_f, &guarantee_ctl, srcGuaranteeEn);
    cmd = DRV_IOW(QWriteGuaranteeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &guarantee_ctl));

    return CTC_E_NONE;
}

int32
sys_usw_port_set_property(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32 value);

STATIC int32 
_sys_usw_port_check_xpipe_mode(uint8 lchip, uint32 gport, uint16 lport, uint32 value)
{
    uint32 old_mode  = 0;
    uint32 xpipe_en  = 0;
    uint32 fast_pfc  = 0;

    if (!DRV_FROM_TMM(lchip) || CTC_IS_MCHAN_PORT(gport))
    {
        return CTC_E_NOT_SUPPORT;
    }
    else if (DRV_FROM_AT(lchip))
    {
        CTC_MAX_VALUE_CHECK(value, CTC_XPIPE_MODE_MAX - 1);
    }
    else
    {
        CTC_MAX_VALUE_CHECK(value, CTC_XPIPE_MODE_3);
    }

    /* need clear prop before cfg */
    CTC_ERROR_RETURN(sys_usw_port_get_property(lchip, gport, CTC_PORT_PROP_XPIPE_MODE, &old_mode));
    if(old_mode == value)
    {
        return CTC_E_EXIST;
    }

    if (DRV_FROM_AT(lchip) && old_mode && value)
    {
        return CTC_E_IN_USE;
    }

    /* need clear fast pfc before cfg */
    if (DRV_FROM_AT(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_port_get_property(lchip, gport, CTC_PORT_PROP_FAST_PFC_EN, &fast_pfc));
        if (fast_pfc && (old_mode != value))
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Xpipe can not cfg egs feature on fast-ecn enable\n");
            return CTC_E_INVALID_CONFIG;
        }
    }

    /* don't need to alloc channel or channel has alloced by xpipe enable */
    xpipe_en = p_usw_port_master[lchip]->port_prop[lport].xpipe_type ? 1 : 0;
    if (xpipe_en && (CTC_XPIPE_MODE_4 == value || CTC_XPIPE_MODE_5 == value))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Xpipe not support enable egs three level with igs feature enable\n");
        return CTC_E_NOT_SUPPORT;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_xpipe_mode(uint8 lchip, uint32 gport, uint32 value)
{
    uint16 lport     = 0;

    /*for TM.MX, only set xpipe en(rx) can alloc and free new channel*/
    if (DRV_FROM_AT(lchip) || DRV_IS_TMG(lchip))
    {
        CTC_ERROR_RETURN(_sys_usw_port_set_dmps_channel(lchip, gport, SYS_PORT_API_DMPS_PROP_XPIPE_TX, value));
    }

    if (MCHIP_PORT(lchip)->port_set_xpipe_mode)
    {
        CTC_ERROR_RETURN(MCHIP_PORT(lchip)->port_set_xpipe_mode(lchip, gport, value));
    }

    /*for TM.MX, disable xpipe mode(tx) means disable xpipe mode(tx) and type(rx)*/
    if( (DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)) && !value && p_usw_port_master[lchip]->port_prop[lport].xpipe_type && MCHIP_PORT(lchip)->port_set_xpipe_en)
    {
        lport = CTC_MAP_GPORT_TO_LPORT(gport);
        CTC_ERROR_RETURN(MCHIP_PORT(lchip)->port_set_xpipe_en(lchip, gport, value));
        p_usw_port_master[lchip]->port_prop[lport].xpipe_type = value;
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);
    }
    return CTC_E_NONE;
}


STATIC int32
_sys_usw_port_get_xpipe_mode(uint8 lchip, uint32 gport, uint32* p_value)
{
    uint32  pp_id        = 0;
    uint8  mac_num       = 0;
    uint8  identify_en   = 0;
    uint8  identify_mode = 0;
    ds_t ds = {0};
    uint32 xpipe_en = 0;
    uint32 pmac_channel_id = 0;
    uint32 mac_id[SYS_USW_MAX_CHANEL_NUM_PER_PORT] = {0};     /* 0: low prio mac, 1: middle prio mac 2: high prio mac(origin mac) */
    uint32 cmd = 0;
    uint32 port_type = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    if (!DRV_FROM_TMM(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }

    dmps_port_info.gport = gport;
    /**Cpu mac use for network port not support xpipe*/
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
    if (SYS_DMPS_NETWORK_PORT != port_type)
    {
        return CTC_E_INVALID_PORT;
    }

    CTC_ERROR_RETURN(sys_usw_port_api_get_mac(lchip, 0, gport, mac_id, &mac_num));
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, (void *)&pmac_channel_id));
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, DRV_FROM_AT(lchip) ? SYS_PORT_API_DMPS_PROP_XPIPE_TX : SYS_PORT_API_DMPS_PROP_XPIPE_RX, &xpipe_en));
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));

    lchip = SYS_PP_BASE(lchip) + pp_id;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "origin mac id: %d, origin channel: %d\n", mac_id[mac_num - 1], pmac_channel_id);

    if (xpipe_en)
    {
        if (DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(DsUcQWriteGuarantee_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, ((pmac_channel_id & 0x1FF) >> 4), DRV_CMD_PP_EN(cmd), ds));

            identify_en   = CTC_IS_BIT_SET(GetDsUcQWriteGuarantee(V, identifyEn_f,   ds), pmac_channel_id & 0xF);
            identify_mode = CTC_IS_BIT_SET(GetDsUcQWriteGuarantee(V, identifyMode_f, ds), pmac_channel_id & 0xF);

            if (identify_en && identify_mode)
            {
                *p_value = (2 == mac_num) ? CTC_XPIPE_MODE_1 : CTC_XPIPE_MODE_5;
            }
            else if(identify_en && !identify_mode)
            {
                *p_value = CTC_XPIPE_MODE_3;
            }
            else
            {
                *p_value = (2 == mac_num) ? CTC_XPIPE_MODE_2 : CTC_XPIPE_MODE_4;
            }
        }
        else
        {
            cmd = DRV_IOR(DsQWriteGuarantee_t, DsQWriteGuarantee_mode_f);
            DRV_FIELD_IOCTL(lchip, pmac_channel_id, cmd, p_value);
            if (0 == *p_value)
            {
                *p_value =CTC_XPIPE_MODE_1;
            }
            else if (1 == *p_value)
            {
                *p_value = CTC_XPIPE_MODE_2;
            }
            else
            {
                *p_value = CTC_XPIPE_MODE_3;
            }
        }
    }
    else
    {
        *p_value = CTC_XPIPE_MODE_0;
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_check_xpipe(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32 value)
{
    uint32 port_type   = 0;
    uint16 lport = 0;
    uint8  trunk_id    = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    if (CTC_MAP_GPORT_TO_LPORT(gport) >= MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP))
    {
        return CTC_E_INVALID_PORT;
    }

    dmps_port_info.gport = gport;
    /**Cpu mac use for network port not support xpipe*/
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
    if ((SYS_DMPS_NETWORK_PORT != port_type))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Gport %u is not a network port! \n", gport);
        return CTC_E_INVALID_PORT;
    }

    /* get trunk id */
    /* alloc channel and cfg stacking property start alloc by xpipe enable/mode */
    CTC_ERROR_RETURN(SYS_CB(SYS_CB_STK_GET_BINDING_TRUNK, lchip, gport, &trunk_id));
    if (trunk_id)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Gport %u is cfg stacking prop! \n", gport);
        return CTC_E_IN_USE;
    }

    lport = CTC_MAP_GPORT_TO_LPORT(gport);
    if (lport >= MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP))
    {
        return CTC_E_INVALID_PORT;
    }

    switch(port_prop)
    {
        case CTC_PORT_PROP_XPIPE_EN:
            CTC_ERROR_RETURN(_sys_usw_port_check_xpipe_type(lchip, gport, lport, value));
            break;

        case CTC_PORT_PROP_XPIPE_MODE:
            CTC_ERROR_RETURN(_sys_usw_port_check_xpipe_mode(lchip, gport, lport, value));
            break;

        default:
            return CTC_E_INVALID_PARAM;

    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_set_fpfc_en(uint8 lchip, uint32 gport, uint32 value)
{
    ds_t ds = {0};
    uint32 channel_id = 0;
    uint32 dp_id = 0;
    uint32 cmd = 0;
    uint16 data = 0;
    uint16 data_old = 0;
    uint8  mac_num = 0;
    uint8 txqm_id = 0;
    uint8 step = 0;
    uint32 tbl_id = 0;
    uint8 tbl_idx = 0;
    uint8 index = 0;
    uint8 tmp_data = 0;
    ctc_register_xpipe_action_t xpipe_action;
    uint32 mode = 0;
    uint32 mac_id[SYS_USW_MAX_CHANEL_NUM_PER_PORT] = {0};     /* 0: low prio mac, 1: middle prio mac 2: high prio mac(origin mac) */
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    if (!DRV_FROM_AT(lchip) || CTC_IS_MCHAN_PORT(gport))
    {
        return CTC_E_NOT_SUPPORT;
    }

    sal_memset(&xpipe_action, 0, sizeof(ctc_register_xpipe_action_t));
    /* only suppotr fast PFC when XPIPE mode is pri + color */
    CTC_ERROR_RETURN(sys_usw_port_get_property(lchip, gport, CTC_PORT_PROP_XPIPE_MODE, &mode));
    if (CTC_XPIPE_MODE_2 != mode && CTC_XPIPE_MODE_4 != mode)
    {
        return CTC_E_INVALID_CONFIG;
    }

    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, &dp_id));
    CTC_ERROR_RETURN(sys_usw_port_api_get_mac(lchip, 1, gport, mac_id, &mac_num));
    if (SYS_DMPS_INVALID_CHAN_ID == channel_id || SYS_DMPS_INVALID_U8 == dp_id || 0 == mac_num)
    {
        return CTC_E_INVALID_PORT;
    }

    /*NetTxPausePriRemap0/1(per dp TXQM0/1)*/
    txqm_id = (mac_id[mac_num-1] / MCHIP_CAP(SYS_CAP_MAX_MAC_NUM_PER_TXQM));
    step = NetTxPausePriRemap1_t - NetTxPausePriRemap0_t;
    tbl_id = NetTxPausePriRemap0_t + txqm_id * step;
    tbl_idx = (mac_id[mac_num-1] % MCHIP_CAP(SYS_CAP_MAX_MAC_NUM_PER_TXQM));
    /*DP*/
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, tbl_idx, DRV_CMD_DP_EN(cmd, dp_id), ds));
    data_old = GetNetTxPausePriRemap0(V, data_f, ds);

    if (value)
    {
        /* sel 2/3 highest priority */
        for (index = 0; index < CTC_CONST16; index += 2)
        {
            xpipe_action.priority = index;
            xpipe_action.color = 0;
            CTC_ERROR_RETURN(sys_usw_global_ctl_get(lchip, CTC_GLOBAL_XPIPE_ACTION, &xpipe_action));
            tmp_data = (xpipe_action.is_high_pri == SYS_PORT_SOURCE_CHAN? SYS_PORT_LOW_PRIO_PORT: \
                   (xpipe_action.is_high_pri ==SYS_PORT_HIGH_PRIO_CHAN || CTC_XPIPE_MODE_2 == mode)? SYS_PORT_SOURCE_PORT: SYS_PORT_HIGH_PRIO_PORT);
            data |= ((tmp_data & 0x3) << index);
        }
    }

    SetNetTxPausePriRemap0(V, data_f, ds, data);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, tbl_idx, DRV_CMD_DP_EN(cmd, dp_id), ds));

    /*change fast_pfc need clear NetTxPauseStallLog0/1*/
    if(data != data_old)
    {
        sal_memset(&ds, 0, sizeof(ds_t));
        step = netTxPauseStallLog1_t - netTxPauseStallLog0_t;
        tbl_id = netTxPauseStallLog0_t + txqm_id * step;
        for (index = 0; index < mac_num; index ++)
        {
            tbl_idx = (mac_id[index] % MCHIP_CAP(SYS_CAP_MAX_MAC_NUM_PER_TXQM));
            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, tbl_idx, DRV_CMD_DP_EN(cmd, dp_id), ds));
        }
    }

    /*set DsUcQWriteGuarantee.mergeEn, pp table cfg all pp */
    cmd = DRV_IOR(DsUcQWriteGuarantee_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, ((channel_id & 0x1FF) >> 4), cmd, ds));
    data = GetDsUcQWriteGuarantee(V, mergeEn_f, ds);
    data = value ? (data & (~(1 << (channel_id & 0xF)))) : (data | (1 << (channel_id & 0xF)));
    SetDsUcQWriteGuarantee(V, mergeEn_f, ds, data);
    cmd = DRV_IOW(DsUcQWriteGuarantee_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, ((channel_id & 0x1FF) >> 4), cmd, ds));

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_fpfc_en(uint8 lchip, uint32 gport, uint32* value)
{
    ds_t ds = {0};
    uint32 cmd = 0;
    uint8 merge_en = 0;
    uint32 mode   = 0;
    uint32 channel= 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    if (!DRV_FROM_AT(lchip) || CTC_IS_MCHAN_PORT(gport))
    {
        return CTC_E_NOT_SUPPORT;
    }

    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_get_property(lchip, gport, CTC_PORT_PROP_XPIPE_MODE, &mode));
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel));

    if (SYS_DMPS_INVALID_CHAN_ID == channel)
    {
        return CTC_E_INVALID_PORT;
    }

    cmd = DRV_IOR(DsUcQWriteGuarantee_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, ((channel & 0x1FF) >> 4), DRV_CMD_PP_EN(cmd), ds));
    merge_en = CTC_IS_BIT_SET(GetDsUcQWriteGuarantee(V, mergeEn_f, ds), channel & 0xF);

    if ((CTC_XPIPE_MODE_2 == mode || CTC_XPIPE_MODE_4 == mode) && !merge_en)
    {
        *value = 1;
    }

    return CTC_E_NONE;
}
int32
sys_usw_port_get_local_phy_port(uint8 lchip, uint32 gport, uint32* p_value)
{
    uint16 lport     = 0;
    uint16 local_phy_port = SYS_INVALID_LOCAL_PHY_PORT;
    uint8  gchip_id = 0;

    lport = SYS_MAP_CTC_GPORT_TO_DRV_LPORT(gport);

    gchip_id = CTC_MAP_GPORT_TO_GCHIP(gport);
    if(sys_usw_chip_is_local(lchip, gchip_id) && !CTC_IS_LINKAGG_PORT(gport))
    {
        local_phy_port = p_usw_port_master[lchip]->network_port[lport];
    }
    *p_value = local_phy_port;

    return CTC_E_NONE;
}

int32
sys_usw_port_lport_convert(uint8 lchip, uint16 internal_lport, uint16* p_value)
{
    uint16 loop = 0;

    for (loop = 0; loop < MCHIP_CAP(SYS_CAP_SPEC_MAX_PHY_PORT_NUM); loop++)
    {
        if (0 == p_usw_port_master[lchip]->port_prop[loop].lbk_en)
        {
            continue;
        }
        if (p_usw_port_master[lchip]->port_prop[loop].inter_lport == internal_lport)
        {
            *p_value = loop;
            break;
        }
    }

    return CTC_E_NONE;
}

int32 sys_usw_port_get_property(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32 * p_value);

/**
@brief   Config port's speed for cut-through
*/
int32 _sys_usw_port_set_cut_through_speed(uint8 lchip, uint32 gport)
{
    uint32 cmd = 0;
    uint32 speed = 0;
    uint16 lport = 0;

    lport = SYS_MAP_CTC_GPORT_TO_DRV_LPORT(gport);
    speed = sys_usw_chip_get_cut_through_speed(lchip, gport);
    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_speed_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &speed));
    cmd = DRV_IOW(DsDestPortSpeed_t, DsDestPortSpeed_speed_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &speed));

    return CTC_E_NONE;
}

int32
sys_usw_port_mac_config_attach(uint8 lchip, sys_usw_port_mac_config_t* port_mac_config)
{
    uint32 gport = 0;
    uint8 gchip = 0;
    uint32 port_type = 0;
    uint32 mac_id = 0;
    uint32 chan_id = 0;
    uint32 cmd = 0;
    uint8 dp_id = 0;
    uint32 step = 0;
    uint32 field_val = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    ds_t ds;

    if(!(DRV_FROM_AT(lchip) && port_mac_config->is_init))
    {
        CTC_ERROR_RETURN(_sys_usw_port_set_xpipe_channel(lchip, port_mac_config->lport));
        CTC_ERROR_RETURN(SYS_CB(SYS_CB_QOS_SET_PORT_DYNAMIC_SWITCH, lchip, port_mac_config->lport, 0));
    }
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
    gport = CTC_MAP_LPORT_TO_GPORT(gchip, port_mac_config->lport);
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
    if(SYS_DMPS_NETWORK_PORT == port_type || SYS_DMPS_CPUMAC_NETWORK_PORT == port_type || SYS_DMPS_CPU_MAC_PORT == port_type)
    {
        if((!(DRV_FROM_AT(lchip) && port_mac_config->is_init)) && MCHIP_PORT(lchip)->port_set_pause_speed)
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, (void *)&mac_id));
            CTC_ERROR_RETURN(MCHIP_PORT(lchip)->port_set_pause_speed(lchip, mac_id, (void*)port_mac_config));
        }
        /*dynamic new port, must set selfhealingset.channelId for mirror to remote port*/
        cmd = DRV_FROM_AT(lchip) ?DRV_IOW(DsMetExcpPortLagLinkSelfHealingSet_t, DsMetExcpPortLagLinkSelfHealingSet_channelId_f) \
                : DRV_IOW(DsMetPortLagLinkSelfHealingSet_t, DsMetPortLagLinkSelfHealingSet_channelId_f);
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &field_val));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, port_mac_config->lport, cmd, &field_val));
        CTC_ERROR_RETURN(sys_usw_dmps_set_dlb_chan_type(lchip, field_val));
    }

    if ((!DRV_FROM_AT(lchip))&&((SYS_DMPS_CPUMAC_NETWORK_PORT == port_type) || (SYS_DMPS_CPU_MAC_PORT == port_type)))
    {
        dp_id = (mac_id - SYS_CPU_MAC_ID_MIN) / MCHIP_CAP(SYS_CAP_CPUMAC_NUM_PER_DP);
        step = (mac_id - SYS_CPU_MAC_ID_MIN) % MCHIP_CAP(SYS_CAP_CPUMAC_NUM_PER_DP);
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
        chan_id = chan_id % MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM);
        cmd = DRV_IOR(NetRxMiscChanIdCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, dp_id, cmd, ds));
        SetNetRxMiscChanIdCfg(V, cfgCpuMacChanId0_f + step , ds,chan_id);
        cmd = DRV_IOW(NetRxMiscChanIdCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, dp_id, cmd, ds));
        return CTC_E_NONE;
    }
    CTC_ERROR_RETURN(_sys_usw_port_set_cut_through_speed(lchip, gport));
    CTC_ERROR_RETURN(_sys_usw_port_set_cut_through_en(lchip, gport, TRUE));

    return CTC_E_NONE;
}

int32
_sys_usw_port_set_property(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32 value)
{
    int32   ret = CTC_E_NONE;
    uint16  lport = 0;
    uint32  field = 0;
    ds_t    ds;
    uint32  efd_en[SYS_USW_MAX_PORT_NUM/32] = {0};
    IpePortEfdCtl_m port_efd_ctl;
    uint32  cmd = 0;
    uint8 step = 0;
    uint32  entry_num = 0;
    uint32  index = 0;
    uint32  channel_id = 0;
    uint32  mac_id = 0;
    uint8   tmp_lchip = 0;
    uint8   hata_ts_format = 0;
    //uint32  speed = 0;
    uint8   is_support_glb_port = _sys_usw_port_is_support_glb_port(lchip);
    uint8   gchip = SYS_MAP_CTC_GPORT_TO_GCHIP(gport);
    uint8   chip_is_dt2ortm = (DRV_IS_DUET2(lchip) || DRV_IS_TSINGMA(lchip));
    uint8   chan_id = 0;
    uint8 idx = 0;
    uint8 is_network = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property, gport:0x%04X, property:%d, value:0x%x\n", \
                     gport, port_prop, value);

    sal_memset(ds, 0, sizeof(ds));
    /*Sanity check*/
    if (port_prop != CTC_PORT_PROP_STATION_MOVE_PRIORITY && port_prop != CTC_PORT_PROP_STATION_MOVE_ACTION)
    {
        SYS_GLOBAL_CHIPID_CHECK(gchip);
    }
    if (FALSE == sys_usw_chip_is_local(lchip, gchip) && port_prop != CTC_PORT_PROP_XPIPE_EN &&
        port_prop != CTC_PORT_PROP_STATION_MOVE_PRIORITY&& port_prop != CTC_PORT_PROP_STATION_MOVE_ACTION)
    {
        return _sys_usw_port_set_global_property(lchip, gport, port_prop, value);
    }
    if (CTC_GPORT_TYPE(gport) == CTC_GPORT_TYPE_DMA)
    {
        return CTC_E_INVALID_PARAM;
    }
    lport = CTC_MAP_GPORT_TO_LPORT(gport);
    if (CTC_GPORT_TYPE(gport) == CTC_GPORT_TYPE_CPU_MAC)
    {
        idx = gport & 0xf;
        if(MCHIP_DMPS(lchip)->cpumac_get_lport_info_by_inner_idx)
        {
            CTC_ERROR_RETURN(MCHIP_DMPS(lchip)->cpumac_get_lport_info_by_inner_idx(lchip,idx,&lport,&is_network));
        }
    }
    else
    {
        lport = SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport);
    }

    dmps_port_info.gport = gport;

    switch (port_prop)
    {
    case CTC_PORT_PROP_NSH_SI_CHECK:
        {
            uint32 check_en_bmp[CTC_B2W_SIZE(MAX_PORT_NUM_PER_CHIP)];
            cmd = DRV_IOR(IpePortNshSiCtl_t, DRV_ENTRY_FLAG);
            ret = DRV_IOCTL(lchip, 0, cmd, &check_en_bmp);
            if (!value)
            {
                CTC_BMP_UNSET(check_en_bmp,lport);
            }
            else
            {
                CTC_BMP_SET(check_en_bmp,lport);
            }
            cmd = DRV_IOW(IpePortNshSiCtl_t, DRV_ENTRY_FLAG);
            ret = ret ? ret : DRV_IOCTL(lchip, 0, cmd, &check_en_bmp);
        }
        break;
    case CTC_PORT_PROP_ESID:
        if (DRV_FROM_TMM(lchip))
        {
            if (value > SYS_PORT_MAX_ESID)
            {
                return CTC_E_INTR_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_mplsEvpnDestEsId_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &value);
        }
        else
        {
            cmd = DRV_IOR(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
            if (!CTC_IS_BIT_SET(field, 1))
            {
                return CTC_E_INVALID_CONFIG;
            }
            CTC_MAX_VALUE_CHECK(value, 0xFF);
            field = value;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_fcoeOuiIndex_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        }
        break;
    case CTC_PORT_PROP_ESLB:
        if (DRV_FROM_TMM(lchip))
        {
            if (value > MCHIP_CAP(SYS_CAP_MPLS_MAX_LABEL))
            {
                return CTC_E_INTR_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsMplsEvpnEsLabel_t, DsMplsEvpnEsLabel_mplsEvpnEsiLabel_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &value);
        }
        else
        {
            cmd = DRV_IOR(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
            if (!CTC_IS_BIT_SET(field, 1) || (value > MCHIP_CAP(SYS_CAP_MPLS_MAX_LABEL)))
            {
                return CTC_E_INVALID_CONFIG;
            }
            field = value&0x7F;
            cmd = DRV_IOW(DsPortLinkAgg_t, DsPortLinkAgg_u1_g1_channelLinkAggregate_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
            field = (value&0x80) >> 7;
            cmd = DRV_IOW(DsPortLinkAgg_t, DsPortLinkAgg_channelLinkAggregateEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
            field = (value&0xFFF00) >> 8;
            cmd = DRV_IOW(DsPortLinkAgg_t, DsPortLinkAgg_ecid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        }
        break;
    case CTC_PORT_PROP_SELECT_MAX_SCL_PRIO_EN:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_sclPrioEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_CLOUDSEC_EN:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_cloudSecEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_HMAC_EN:
        if (!DRV_FLD_IS_EXISIT(DsPhyPortExt_t, DsPhyPortExt_hmacCheckEn_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_hmacCheckEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_WLAN_DECAP_WITH_RID:
        if (!DRV_FLD_IS_EXISIT(DsPhyPortExt_t, DsPhyPortExt_radioMacType_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        field = value ? 1 : 0;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_radioMacType_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_DISCARD_UNENCRYPT_PKT:
        if (!DRV_FLD_IS_EXISIT(DsPhyPortExt_t, DsPhyPortExt_discardPlainTextPacket_f))
        {
            return CTC_E_NOT_SUPPORT;
        } 
        field = value ? 1 : 0;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_discardPlainTextPacket_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_RAW_PKT_TYPE:
        ret = _sys_usw_port_set_raw_packet_type(lchip, gport, value);
        break;

    case CTC_PORT_PROP_VLAN_DOMAIN:
        CTC_MAX_VALUE_CHECK(value, CTC_PORT_VLAN_DOMAIN_MAX - 1);
        field = (CTC_PORT_VLAN_DOMAIN_CVLAN == value) ? 1 : 0;

        cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_outerVlanIsCVlan_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_cvlanSpace_f):DRV_IOW(DsDestPort_t, DsDestPort_cvlanSpace_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_flowL2KeyUseCvlan_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_flowL2KeyUseCvlan_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        cmd = chip_is_dt2ortm ?  DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_sclFlowL2KeyUseCvlan_f) :
                DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_sclFlowL2KeyUseCvlan_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_PORT_EN:
        if (value)
        {
            if(MCHIP_DMPS(lchip)->mac_link_up_event)
            {
                ret = MCHIP_DMPS(lchip)->mac_link_up_event(lchip, lport);
            }
        }
        else
        {
            if(MCHIP_DMPS(lchip)->mac_link_down_event)
            {
                ret = MCHIP_DMPS(lchip)->mac_link_down_event(lchip, lport);
            }
        }
        ret = ret ? ret : _sys_usw_port_set_port_en(lchip, gport, value);
        break;

    case CTC_PORT_PROP_TRANSMIT_EN:     /**< set port whether the tranmist is enable */
        field = (value) ? 0 : 1;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_transmitDisable_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
                CTC_ERROR_RETURN(_sys_usw_port_set_mcast_member_down(lchip, gport, (value) ? 0 : 1));
        break;

    case CTC_PORT_PROP_RECEIVE_EN:      /**< set port whether the receive is enable */
        field = (value) ? 0 : 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_receiveDisable_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_BRIDGE_EN:       /**< set port whehter layer2 bridge function is enable */
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_bridgeEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        field = (value) ? 1 : 0;

        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_bridgeEn_f):DRV_IOW(DsDestPort_t, DsDestPort_bridgeEn_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_DEFAULT_VLAN:     /**< set default vlan id of packet which receive from this port */
        if (value < CTC_MIN_VLAN_ID || value > CTC_MAX_VLAN_ID)
        {
            return CTC_E_INVALID_PARAM;
        }
        ret = _sys_usw_port_set_default_vlan(lchip, gport, value);
        break;

    case CTC_PORT_PROP_UNTAG_PVID_TYPE:
        switch(value)
        {
        case CTC_PORT_UNTAG_PVID_TYPE_NONE:
            field = 0;
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultVlanId_f):DRV_IOW(DsDestPort_t, DsDestPort_untagDefaultVlanId_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
            break;

        case CTC_PORT_UNTAG_PVID_TYPE_SVLAN:
            field = 1;
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultVlanId_f):DRV_IOW(DsDestPort_t, DsDestPort_untagDefaultVlanId_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
            field = 1;
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultSvlan_f):DRV_IOW(DsDestPort_t, DsDestPort_untagDefaultSvlan_f);
            ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
            break;

        case CTC_PORT_UNTAG_PVID_TYPE_CVLAN:
            field = 1;
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultVlanId_f):DRV_IOW(DsDestPort_t, DsDestPort_untagDefaultVlanId_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
            field = 0;
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_untagDefaultSvlan_f):DRV_IOW(DsDestPort_t, DsDestPort_untagDefaultSvlan_f);
            ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
            break;

        default:
            return CTC_E_INVALID_PARAM;
        }
        break;

    case CTC_PORT_PROP_VLAN_CTL:     /**< set port's vlan tag control mode */
        if (value >= MAX_CTC_VLANTAG_CTL)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_vlanTagCtl_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_CROSS_CONNECT_EN:     /**< Set port cross connect */
        ret = _sys_usw_port_set_cross_connect(lchip, gport, value);
        break;

    case CTC_PORT_PROP_LEARNING_EN:     /**< Set learning enable/disable on port */
        field = (value) ? 0 : 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_learningDisable_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_LEARN_DIS_MODE:
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_learningDisableMode_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        field = value? 1: 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_learningDisableMode_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_FORCE_MPLS_EN:
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_openflowMplsEn_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        field = value? 1: 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_openflowMplsEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_FORCE_TUNNEL_EN:
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_openflowTunnelEn_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        field = value? 1: 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_openflowTunnelEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_DOT1Q_TYPE:     /**< Set port dot1q type */
        if (value > CTC_DOT1Q_TYPE_BOTH)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dot1QEn_f): DRV_IOW(DsDestPort_t, DsDestPort_dot1QEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_USE_OUTER_TTL:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_useOuterTtl_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_PROTOCOL_VLAN_EN:     /**< set protocol vlan enable on port */
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_protocolVlanEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_SRC_DISCARD_EN:     /**< set port whether the src_discard is enable */
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_srcDiscard_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_PORT_CHECK_EN:     /**< set port whether the src port match check is enable */
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portCheckEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_HW_LEARN_EN:     /**< Hardware learning enable*/
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_fastLearningEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_SCL_IPV6_LOOKUP_EN:
        ret = CTC_E_NOT_SUPPORT;
        break;

    case CTC_PORT_PROP_SCL_IPV4_LOOKUP_EN:
        ret = CTC_E_NOT_SUPPORT;
        break;

    case CTC_PORT_PROP_SCL_USE_DEFAULT_LOOKUP:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_useDefaultVlanLookup_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_SCL_FORCE_IPV6_TO_MAC:
        ret = CTC_E_NOT_SUPPORT;
        break;

    case CTC_PORT_PROP_SCL_FORCE_IPV4_TO_MAC:
        ret = CTC_E_NOT_SUPPORT;
        break;

    case CTC_PORT_PROP_TRILL_EN:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_trillEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_TRILL_MCAST_DECAP_EN:
        field = (value) ? 1 : 0;
        cmd = chip_is_dt2ortm ?  DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_trillMcastLoopback_f) :
                    DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_trillMcastLoopback_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_DISCARD_NON_TRIL_PKT:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_discardNonTrill_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_DISCARD_TRIL_PKT:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_discardTrill_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_REFLECTIVE_BRIDGE_EN:
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

        field = value ? 0 : 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portCheckEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);

        field = value ? 1 : 0;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_reflectiveBridgeEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        if (!(CTC_IS_BIT_SET(value, (CTC_CONST32 - 1))))
        {
            ret = ret ? ret : _sys_usw_port_set_port_reflective(lchip, lport, value ? 1 : 0);
        }
        break;

    case CTC_PORT_PROP_FCOE_EN:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_fcoeEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_RPF_EN:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedRpfEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_FCMAP:
        cmd = DRV_IOR(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
        DRV_FIELD_IOCTL(lchip, 0, cmd, &field);
        if (CTC_IS_BIT_SET(field, 1) && DRV_IS_TSINGMA(lchip))
        {
            return CTC_E_INVALID_CONFIG;
        }
        if (value < 0x0EFC00 || value > 0x0EFCFF)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value & 0xFF;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_fcoeOuiIndex_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_REPLACE_STAG_COS:
        field = (value) ? 1 : 0;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_replaceStagCos_f):DRV_IOW(DsDestPort_t, DsDestPort_replaceStagCos_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_REPLACE_STAG_TPID:
        field = (value) ? 1 : 0;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_replaceStagTpid_f):DRV_IOW(DsDestPort_t, DsDestPort_replaceStagTpid_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_REPLACE_CTAG_COS:
        field = (value) ? 1 : 0;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_replaceCtagCos_f):DRV_IOW(DsDestPort_t, DsDestPort_replaceCtagCos_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_REPLACE_DSCP_EN:
        field = (value) ? 2 : 0;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dscpRemarkMode_f):DRV_IOW(DsDestPort_t, DsDestPort_dscpRemarkMode_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_L3PDU_ARP_ACTION:
        if (value >= CTC_PORT_ARP_ACTION_TYPE_MAX)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_arpExceptionType_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_L3PDU_DHCP_ACTION:
        if (value >= CTC_PORT_DHCP_ACTION_TYPE_MAX)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_dhcpV4ExceptionType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        field = value;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_dhcpV6ExceptionType_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_L3PDU_DHCP_V6_ACTION:
        if (value >= CTC_PORT_DHCP_ACTION_TYPE_MAX)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOR(DsSrcPort_t,DRV_ENTRY_FLAG);
        ret = DRV_IOCTL(lchip, lport, cmd, &ds);
        SetDsSrcPort(V, dhcpV6ExceptionType_f,&ds,field);
        cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
        ret = ret ? ret : (DRV_IOCTL(lchip, lport, cmd, &ds));
        break;

    case CTC_PORT_PROP_TUNNEL_RPF_CHECK:
        field = (value) ? 1 : 0;
        cmd = chip_is_dt2ortm ?  DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_tunnelRpfCheck_f) :
        DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_tunnelRpfCheck_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_PTP_EN:
        if (value > MCHIP_CAP(SYS_CAP_PTP_MAX_PTP_ID))
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_ptpIndex_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        /* udp checksum update just for TM1.1 */
        if ((SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_B) && DRV_IS_TSINGMA(lchip))
        {
            cmd = DRV_IOR(DsDestPortChannelMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));
            chan_id = GetDsDestPortChannelMap(V, channelId_f, &ds);
            if (chan_id >= MCHIP_CAP(SYS_CAP_NETWORK_CHANNEL_NUM))
            {
                return CTC_E_INVALID_PORT;
            }
            cmd = DRV_IOR(EpeHeaderAdjustPhyPortMap_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, chan_id, cmd, &ds));
            lport = GetEpeHeaderAdjustPhyPortMap(V, localPhyPort_f, &ds);
            gport = CTC_MAP_LPORT_TO_GPORT(gchip, lport);

            field = value ? 1 : 0;
            ret = ret ? ret : sys_usw_dmps_set_port_property(lchip, gport, SYS_PORT_API_DMPS_PROP_TX_CHKSUM_UPD_EN, &field);
        }

        break;

    case CTC_PORT_PROP_PTP_DOMAIN_ID:
        if(!DRV_IS_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        /*IPE/EPE*/
        if (value > MCHIP_CAP(SYS_CAP_PTP_MAX_DOMAIN_ID))
        {
            return CTC_E_INVALID_PARAM;
        }
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
        if (!SYS_IS_NETWORK_CHANNEL(channel_id))
        {
            return CTC_E_INVALID_PARAM;
        }

        p_usw_port_master[lchip]->port_prop[lport].ptp_domain_id = value;
        value = value? MCHIP_CAP(SYS_CAP_PTP_DOMAIN_1_RTC) : MCHIP_CAP(SYS_CAP_PTP_DOMAIN_0_RTC);

        cmd = DRV_IOR(DsSrcChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));
        SetDsSrcChannel(V,todRtcId_f,&ds,value);
        SetDsSrcChannel(V,macSelectTsFormat_f,&ds,1);
        cmd = DRV_IOW(DsSrcChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));

        cmd = DRV_IOR(DsDestChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));
        SetDsDestChannel(V,todRtcId_f,&ds,value);
        SetDsDestChannel(V,ptpTcIngressTsFormat_f,&ds,1);
        SetDsDestChannel(V,ptpCpuIngressTsFormat_f,&ds,1);
        cmd = DRV_IOW(DsDestChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));

        /*MacRx/MacTx*/
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, &mac_id));
        mac_id = mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_DP);
        SYS_MAP_GPORT_TO_LCHIP1(gport, tmp_lchip);

        /*HataRx/HataTx*/
        step = McHataRxCfg_cfgHataRxTodRtcId1_f - McHataRxCfg_cfgHataRxTodRtcId0_f;
        cmd = DRV_IOR(McHataRxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(tmp_lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));
        hata_ts_format = GetMcHataRxCfg(V, cfgHataRxSelTsFormat_f, &ds);
        CTC_BIT_SET(hata_ts_format, step*(mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM)));
        SetMcHataRxCfg(V, cfgHataRxTodRtcId0_f + step*(mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM)), &ds, value);
        SetMcHataRxCfg(V, cfgHataRxSelTsFormat_f, &ds, hata_ts_format);
        cmd = DRV_IOW(McHataRxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(tmp_lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));

        cmd = DRV_IOR(McHataTxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(tmp_lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));
        hata_ts_format = GetMcHataTxCfg(V, cfgHataTxSelTsFormat_f, &ds);
        CTC_BIT_SET(hata_ts_format, step*(mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM)));
        SetMcHataTxCfg(V, cfgHataTxTodRtcId0_f + step*(mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM)), &ds, value);
        SetMcHataTxCfg(V, cfgHataTxSelTsFormat_f, &ds, hata_ts_format);
        cmd = DRV_IOW(McHataTxCfg_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(tmp_lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));
        break;
    case CTC_PORT_PROP_RPF_TYPE:
        if (value >= CTC_PORT_RPF_TYPE_MAX)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_rpfType_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_IS_LEAF:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_isLeaf_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_PKT_TAG_HIGH_PRIORITY:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_ingressTagHighPriority_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_ROUTE_EN:
        field = (value) ? 0 : 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_routeDisable_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_PRIORITY_TAG_EN:
        field = (value) ? 1 : 0;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_priorityTagEn_f):DRV_IOW(DsDestPort_t, DsDestPort_priorityTagEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_IPG:
        if (value >= CTC_IPG_SIZE_MAX)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_ipgIndex_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_ipgIndex_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &value);

        {
            uint32 pp_id = 0;
            uint32 dp_id = 0;
            uint32 dp_chan = 0;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SUB_CHAN_ID, &dp_chan));
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, &dp_id));
            cmd = DRV_IOR(IpeIpgCtl_t, IpeIpgCtl_array_0_ipg_f + (IpeIpgCtl_array_1_ipg_f - IpeIpgCtl_array_0_ipg_f)*value);
            ret = ret ? ret : DRV_FIELD_IOCTL(lchip, 0, cmd, &field);
            cmd = DRV_IOW(DsQMgrRdChanCfg_t, DsQMgrRdChanCfg_netLenAdj_f);
            pp_id += SYS_PP_BASE(lchip);
            ret = ret ? ret : DRV_FIELD_IOCTL(pp_id, dp_chan + MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM) * dp_id, DRV_CMD_PP_EN(cmd), &field);
        }
        break;

    case CTC_PORT_PROP_DEFAULT_PCP:
        if (value > 7)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultPcp_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        field = value;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultPcp_f):DRV_IOW(DsDestPort_t, DsDestPort_defaultPcp_f);
        ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_DEFAULT_DEI:
        if (value > 1)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultDei_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);

        field = value;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultDei_f):DRV_IOW(DsDestPort_t, DsDestPort_defaultDei_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_NVGRE_MCAST_NO_DECAP:
        if (value > 1)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = chip_is_dt2ortm ? DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_nvgreMcastLoopbackMode_f) :
        DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_nvgreMcastLoopbackMode_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_VXLAN_MCAST_NO_DECAP:
        if (value > 1)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = chip_is_dt2ortm ? DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_vxlanMcastLoopbackMode_f) :
        DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_vxlanMcastLoopbackMode_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_IP_TUNNEL_MCAST_NO_DECAP:
        if (value > 1)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = (value) ? 0 : 1;
        cmd =  chip_is_dt2ortm ? DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_mcastVpnLoopback_f) :
        DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_mcastVpnLoopback_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);

        cmd =  chip_is_dt2ortm ? DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_v6McastVpnLoopback_f) :
        DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_v6McastVpnLoopback_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_QOS_POLICY:
        if (value >= CTC_QOS_TRUST_MAX)
        {
            return CTC_E_INVALID_PARAM;
        }
        ret  = _sys_usw_port_map_qos_policy(lchip, value, lport);

        break;

    case CTC_PORT_PROP_SCL_HASH_FIELD_SEL_ID:
        if (value > MCHIP_CAP(SYS_CAP_SCL_HASH_SEL_ID_NUM)-1)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = chip_is_dt2ortm ? DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_sclFlowHashFieldSel_f) :
        DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_sclFlowHashFieldSel_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_SNOOPING_PARSER:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_forceSecondParser_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_FLOW_LKUP_BY_OUTER_HEAD:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_aclQosUseOuterInfo_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_IPFIX_LKUP_BY_OUTER_HEAD:
        field = (value) ? 1 : 0;
        cmd = DRV_FROM_TMM(lchip) ? DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_ipfixUseOuterInfo_f) :
                    DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_ipfixAndMicroflowUseOuterInfo_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        if (DRV_FLD_IS_EXISIT(DsDestPort_t, DsDestPort_ipfixUseInnerInfo_f))
        {
            field = (value) ? 0 : 1;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_ipfixUseInnerInfo_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        }
        break;

    case CTC_PORT_PROP_AWARE_TUNNEL_INFO_EN:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_aclKeyMergeInnerAndOuterHdr_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_IPFIX_AWARE_TUNNEL_INFO_EN:
        field = (value) ? 1 : 0;
        cmd = chip_is_dt2ortm ?  DRV_IOW(DsSrcPort_t, DsSrcPort_ipfixAndMicroflowMergeHdr_f) :
        DRV_IOW(DsSrcPort_t, DsSrcPort_ipfixMergeHdr_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        if (DRV_FLD_IS_EXISIT(DsDestPort_t, DsDestPort_ipfixMergeHdr_f))
        {
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_ipfixMergeHdr_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        }
        break;

    case CTC_PORT_PROP_NVGRE_ENABLE:
        field = (value) ? 1 : 0;
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_nvgreEnable_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        }
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_nvgreEnable_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);

        break;

    case CTC_PORT_PROP_METADATA_OVERWRITE_PORT:
        field = (value) ? 3 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_0_aclUseGlobalPortType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_1_aclUseGlobalPortType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_2_aclUseGlobalPortType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_3_aclUseGlobalPortType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        break;

    case CTC_PORT_PROP_METADATA_OVERWRITE_UDF:
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " API or some feature is not supported \n");
        return CTC_E_NOT_SUPPORT;

        break;

    case CTC_PORT_PROP_SRC_MISMATCH_EXCEPTION_EN:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_srcMismatchExceptionEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_STATION_MOVE_PRIORITY:
    {
        uint8 station_move_mode = 0;
        sys_usw_global_get_station_move_mode(lchip, &station_move_mode);
        CTC_MAX_VALUE_CHECK(value, station_move_mode? 0xF : 1);
        field = value;

        if (station_move_mode && sys_usw_chip_is_local(lchip, gchip))
        {
            ds_t ds;
            uint16 cid = 0 ;
            cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));
            cid = GetDsSrcPort(V, categoryId_f, ds);
            cid = (value << 12) | (cid&0xFFF);
            SetDsSrcPort(V, categoryId_f, ds, cid);
            SetDsSrcPort(V, categoryIdValid_f, ds, (cid ? 1:0));
            cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));
        }
        break;
    }

    case CTC_PORT_PROP_STATION_MOVE_ACTION:
    {
        CTC_MAX_VALUE_CHECK(value, CTC_PORT_STATION_MOVE_ACTION_TYPE_MAX-1);
        field = (value == CTC_PORT_STATION_MOVE_ACTION_TYPE_DISCARD_TOCPU) ? 1 : 0;
        if (field && !sys_usw_chip_is_local(lchip, gchip))
        {
            return CTC_E_NOT_SUPPORT;
        }

        if (sys_usw_chip_is_local(lchip, gchip))
        {
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_srcMismatchExceptionEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, CTC_MAP_GPORT_TO_LPORT(gport), cmd, &field));
        }
        break;
    }

    case CTC_PORT_PROP_EFD_EN:
        field = (value) ? 1 : 0;
        if(!DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOW(IpePortEfdCtl_t, IpePortEfdCtl_array_0_efdEnable_f + lport);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field));
        }
        else
        {
            cmd = DRV_IOR(IpePortEfdCtl_t, DRV_ENTRY_FLAG);/*AT*/
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &port_efd_ctl));
            GetIpePortEfdCtl(A, portEfdEnable_f, &port_efd_ctl, efd_en);
            if(value)
            {
                CTC_BMP_SET(efd_en, lport);
            }
            else
            {
                CTC_BMP_UNSET(efd_en, lport);
            }
            SetIpePortEfdCtl(A, portEfdEnable_f, &port_efd_ctl, efd_en);
            cmd = DRV_IOW(IpePortEfdCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &port_efd_ctl));
        }
        break;

    case CTC_PORT_PROP_ADD_DEFAULT_VLAN_DIS:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_addDefaultVlanDisable_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_LOGIC_PORT:
        if (!value)
        {
            field  = 0;
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_useDefaultLogicSrcPort_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);

            field = 0;
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultLogicSrcPort_f);
            ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);

            field  = 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_logicDestPort_f);
            ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        }
        else
        {
            if (value > ((DRV_IS_DUET2(lchip)? 0x3FFF: 0xFFFF)))
            {
                return CTC_E_INVALID_PARAM;
            }
            field  = 1;
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_useDefaultLogicSrcPort_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);

            field = value;
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultLogicSrcPort_f);
            ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);

            field  = value;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_logicDestPort_f);
            ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        }

        break;

    case CTC_PORT_PROP_GPORT:

        ret = _sys_usw_port_set_global_port(lchip, lport, value, FALSE);
        break;

    case CTC_PORT_PROP_LOGIC_PORT_CHECK_EN:

        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_logicPortCheckEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;

    case CTC_PORT_PROP_APS_FAILOVER_EN:
        if (DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        value = (value) ? 1 : 0;
        ret = _sys_usw_port_set_aps_failover_en(lchip, gport, value);
        break;

    case CTC_PORT_PROP_LINKAGG_FAILOVER_EN:
        value = (value) ? 1 : 0;
        ret = _sys_usw_port_set_linkagg_failover_en(lchip, gport, value);
        break;

    case CTC_PORT_PROP_APS_SELECT_GRP_ID:
        if (0xFFFFFFFF == value)
        {
            field = 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_apsSelectValid_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        }
        else
        {
            sys_usw_ftm_query_table_entry_num(lchip, DRV_FROM_AT(lchip)?DsIpeApsBridge_t : DsApsBridge_t, &entry_num);

            if (value >= entry_num)
            {
                ret = CTC_E_BADID;
            }
            else
            {
                field = value;
                cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_apsSelectGroupId_f);
                ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
                field = 1;
                cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_apsSelectValid_f);
                ret = ret ? ret : DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
            }
        }
        break;

    case CTC_PORT_PROP_APS_SELECT_WORKING:
        field = (value) ? 0 : 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_apsSelectProtectingPath_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_CID:
        {
            ds_t ds_port;
            uint16 cid = 0;
            uint8 station_move_mode = 0;
            sys_usw_global_get_station_move_mode(lchip, &station_move_mode);
            if ( ((value) == CTC_ACL_UNKNOWN_CID && !DRV_FROM_TMM(lchip)) || 
                ((value) > ( MCHIP_CAP(SYS_CAP_ACL_MAX_CID_VALUE) >> (station_move_mode? 4 : 0))))
            {
                return CTC_E_BADID;
            }

            cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
            ret = DRV_IOCTL(lchip, lport, cmd, &ds_port);
            cid = GetDsSrcPort(V, categoryId_f, ds_port);
            cid = station_move_mode? ((cid&0xF000) | value) : value;
            SetDsSrcPort(V, categoryId_f, ds_port, cid);
            cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
            ret = DRV_IOCTL(lchip, lport, cmd, &ds_port);   

            field = ((cid&0xF000) | value)? 1 : 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_categoryIdValid_f);
            ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        }
        break;
    case CTC_PORT_PROP_TX_CID_HDR_EN:
        field = (value)?1:0;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_withCidHeader_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        break;
    case CTC_PORT_PROP_WLAN_PORT_TYPE:
        ret = _sys_usw_port_set_wlan_port_type(lchip, gport, value);
        break;
    case CTC_PORT_PROP_WLAN_PORT_ROUTE_EN:
        if (DRV_FROM_TMM(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        ret = _sys_usw_port_set_wlan_port_route(lchip, gport, value);
        break;
    case CTC_PORT_PROP_DSCP_SELECT_MODE:
        if (value > (MAX_CTC_DSCP_SELECT_MODE - 1))
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dscpRemarkMode_f):DRV_IOW(DsDestPort_t, DsDestPort_dscpRemarkMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        break;
    case CTC_PORT_PROP_DEFAULT_DSCP:
        if (value > CTC_MAX_QOS_DSCP_VALUE)
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_defaultDscp_f):DRV_IOW(DsDestPort_t, DsDestPort_defaultDscp_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        break;

    case CTC_PORT_PROP_REPLACE_PCP_DEI:
        field = value ? 1 : 0;
        cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_replacePortPcp_f):DRV_IOW(DsDestPort_t, DsDestPort_replacePortPcp_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        break;
    case CTC_PORT_PROP_CUT_THROUGH_EN:
        #if 0
        /*AT_TODO*/
        cmd = DRV_IOR(DsDestPortSpeed_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));
        speed = GetDsDestPortSpeed(V, speed_f, &ds);
        if (DRV_FROM_TMM(lchip) && 0 == speed)
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "cut through isn't support in profile\n");
            return CTC_E_NOT_SUPPORT;
        }
        #endif
        ret = _sys_usw_port_set_cut_through_en(lchip,gport,value);
        break;
    case CTC_PORT_PROP_SD_ACTION:
        ret = _sys_usw_port_set_sd_action(lchip, CTC_BOTH_DIRECTION, lport, value);
        break;

    case CTC_PORT_PROP_LOOP_WITH_SRC_PORT:
        field = (value) ? 1 : 0;
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_sourcePortToHeader_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_LB_HASH_ECMP_PROFILE:
        if (value > MCHIP_CAP(SYS_CAP_LB_HASH_PROFILE_ID_MAX))
        {
            return CTC_E_INVALID_PARAM;
        }
        field =  value?1:0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedHashProfile0Valid_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedHashProfileId0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        break;
    case CTC_PORT_PROP_LB_HASH_LAG_PROFILE:
        if (value > MCHIP_CAP(SYS_CAP_LB_HASH_PROFILE_ID_MAX))
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value?1:0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedHashProfile1Valid_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedHashProfileId1_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        break;
    case CTC_PORT_PROP_LB_HASH_PROFILE:
        if (value > MCHIP_CAP(SYS_CAP_LB_HASH_PROFILE_ID_MAX))
        {
            return CTC_E_INVALID_PARAM;
        }
        field = value?1:0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedHashProfile0Valid_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedHashProfileId0_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedHashProfile1Valid_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_portBasedHashProfileId1_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        break;
    case CTC_PORT_PROP_DENY_LEARNING :
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_denyLearning_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        value = (value) ? 1 : 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_denyLearning_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        break;
    case CTC_PORT_PROP_UDF_CLASSID:
        if (!DRV_FLD_IS_EXISIT(DsPhyPort_t, DsPhyPort_udfLabel_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        SYS_USW_MAX_CLASS_ID_CHECK(value);
        cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_udfLabel_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &value);
        break;
    case CTC_PORT_PROP_XPIPE_EN:
        SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
        CTC_ERROR_RETURN(_sys_usw_port_set_xpipe_enable(lchip,gport, value));
        break;
    case CTC_PORT_PROP_XPIPE_MODE:
        SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
        CTC_ERROR_RETURN(_sys_usw_port_set_xpipe_mode(lchip, gport, value));
        break;
    case CTC_PORT_PROP_FAST_PFC_EN:
        SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
        CTC_ERROR_RETURN(_sys_usw_port_set_fpfc_en(lchip, gport, value));
        break;
    case CTC_PORT_PROP_QOS_WRR_EN:
        field = (value) ? 1 : 0;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &index));
        if (!SYS_IS_NETWORK_CHANNEL(index))
        {
            return CTC_E_INVALID_PARAM;
        }
        cmd = DRV_IOW(DsQMgrNetSchPpsCfg_t, DsQMgrNetSchPpsCfg_ppsMode_f);
        CTC_ERROR_RETURN(SYS_CB_RET(DRV_FIELD_IOCTL(lchip, index, cmd, &field), SYS_CB_QOS_WRR_EN, lchip, gport, &field, TRUE));
        break;
    case CTC_PORT_PROP_INBAND_CPU_TRAFFIC_EN:
        return CTC_E_NOT_SUPPORT;
    case CTC_PORT_PROP_MUX_TYPE:
        ret = _sys_usw_port_set_mux_type(lchip, gport, value);
        break;
    case CTC_PORT_PROP_STK_GRP_ID:
        CTC_MAX_VALUE_CHECK(value, 7);
        field = value;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_cFlexFwdSgGroupSel_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        field = 1;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_cFlexFwdSgGroupSelEn_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &field);
        break;
    case CTC_PORT_PROP_LB_HASH_VALUE:
        CTC_MAX_VALUE_CHECK(value, 15);
        field = value;
        if(DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOW(IpeFwdIngressPortLbnCtl_t, (IpeFwdIngressPortLbnCtl_gPort_0_lbn_f + (lport & 0x7)));
            ret = DRV_FIELD_IOCTL(lchip, (lport>>3), cmd, &field);
        }
        else 
        {
            cmd = DRV_IOW(IpeFwdIngressPortLbnCtl_t, IpeFwdIngressPortLbnCtl_gPort_0_lbn_f + lport);
            ret = DRV_FIELD_IOCTL(lchip, 0, cmd, &field);
        }
        break;
    case CTC_PORT_PROP_SFD_EN:
        if (DRV_IS_TMM(lchip) && (SYS_GET_CHIP_VERSION == SYS_CHIP_SUB_VERSION_A))
        {
            return CTC_E_NOT_SUPPORT;
        }
        value = value ? 0 : 1;
        ret = sys_usw_dmps_set_port_property(lchip, gport, SYS_PORT_API_DMPS_PROP_SFD_ENABLE, (void*)&value);
        break;

    case CTC_PORT_PROP_MAX_FRAME_SIZE:
    case CTC_PORT_PROP_MIN_FRAME_SIZE:
        if(MCHIP_PORT(lchip)->port_set_property)
        {
            ret = MCHIP_PORT(lchip)->port_set_property(lchip, gport, port_prop, value);
        }
        else
        {
            return CTC_E_INVALID_PTR;
        }
        break;
    case CTC_PORT_PROP_SWAP_CHANNEL:
        sys_usw_port_set_port_swap(lchip, gport, value);
        break;
    case CTC_PORT_PROP_OBM_DSCP_DOMAIN:
    case CTC_PORT_PROP_OBM_COS_DOMAIN:
    case CTC_PORT_PROP_OBM_DEFAULT_PCP:
        CTC_ERROR_RETURN(_sys_usw_port_set_obm_domain(lchip, port_prop, gport, lport, value));
        break;
    case CTC_PORT_PROP_OBM_POLICY:
        if (value >= CTC_QOS_TRUST_MAX)
        {
            return CTC_E_INVALID_PARAM;
        }
        ret  = _sys_usw_port_map_obm_policy(lchip, value, gport, lport);
        break;
    case CTC_PORT_PROP_TRUNCATION_EN:
        {
            uint32 port_type;
            uint32 truncate_bitmap[8];
            uint16 chan_tmp = 0;
            EpeHeaderEditTruncationCtl_m truncationctl;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, &port_type));
            if(port_type != SYS_DMPS_NETWORK_PORT && port_type != SYS_DMPS_DMA_PORT && port_type != SYS_DMPS_OAM_PORT && port_type != SYS_DMPS_CPU_MAC_PORT && port_type != SYS_DMPS_CPUMAC_NETWORK_PORT)
            {
                return CTC_E_INVALID_PORT;
            }
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
            chan_tmp =  SYS_USW_CHANNEL_ENCODE(channel_id); /* for TMG, chan bit7 is dpid, bit6 is not use */
            cmd = DRV_IOR(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
            GetEpeHeaderEditTruncationCtl(A, cfgTruncationEn_f, &truncationctl, truncate_bitmap);
            if(value)
            {
                CTC_BMP_SET(truncate_bitmap, chan_tmp);
            }
            else
            {
                CTC_BMP_UNSET(truncate_bitmap, chan_tmp);
            }
            SetEpeHeaderEditTruncationCtl(A, cfgTruncationEn_f, &truncationctl, truncate_bitmap);
            cmd = DRV_IOW(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
        }
        break;
    default:
        return CTC_E_NOT_SUPPORT;
    }

    if (ret != CTC_E_NONE)
    {
        return ret;
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_property(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32 value)
{
    int32 ret = 0;
    uint32 lport = 0;
    uint32 cmd = 0;
    uint32 dsfwd_offset = 0;

    if (CTC_PORT_PROP_CROSS_CONNECT_EN == port_prop)
    {
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
        if (SYS_NH_INVALID_NHID != value)
        {
            CTC_ERROR_RETURN(sys_usw_nh_get_dsfwd_offset(lchip, value, &dsfwd_offset, 0, CTC_FEATURE_PORT));
        }
    }
    ret = _sys_usw_port_set_property(lchip, gport, port_prop, value);
    if (CTC_PORT_PROP_CROSS_CONNECT_EN == port_prop)
    {
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_u1_g2_dsFwdPtr_f);
        ret = ret? ret: DRV_FIELD_IOCTL(lchip, lport, cmd, &dsfwd_offset);
    }
    if (ret < 0)
    {
        return ret;
    }

    return CTC_E_NONE;
}

/**
@brief    Get port's properties according to gport id
*/
int32
sys_usw_port_get_property(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32* p_value)
{
    uint8  inverse_value = 0;
    int32  ret = CTC_E_NONE;
    uint32  efd_en[SYS_USW_MAX_PORT_NUM/32] = {0};
    IpePortEfdCtl_m port_efd_ctl;
    uint32 cmd = 0;
    uint16 lport = 0;
    uint32 index = 0;
    uint32 value = 0;
    uint8   is_support_glb_port = _sys_usw_port_is_support_glb_port(lchip);
    uint8   gchip = SYS_MAP_CTC_GPORT_TO_GCHIP(gport);
    uint8   chip_is_dt2ortm = (DRV_IS_DUET2(lchip) || DRV_IS_TSINGMA(lchip));
    uint32  port_type = 0;
    uint32 chan_id = 0;
    uint8 idx = 0;
    uint8 is_network = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port property, gport:0x%04X, property:%d!\n", gport, port_prop);

    /*Sanity check*/
    if (port_prop != CTC_PORT_PROP_STATION_MOVE_PRIORITY && port_prop != CTC_PORT_PROP_STATION_MOVE_ACTION)
    {
        SYS_GLOBAL_CHIPID_CHECK(gchip);
    }

    if (FALSE == sys_usw_chip_is_local(lchip, gchip) && port_prop != CTC_PORT_PROP_STATION_MOVE_PRIORITY&& port_prop != CTC_PORT_PROP_STATION_MOVE_ACTION)
    {
        return _sys_usw_port_get_global_property(lchip, gport, port_prop, p_value);
    }
    if (CTC_GPORT_TYPE(gport) == CTC_GPORT_TYPE_DMA)
    {
        return CTC_E_INVALID_PARAM;
    }
    lport = CTC_MAP_GPORT_TO_LPORT(gport);
    if (CTC_GPORT_TYPE(gport) == CTC_GPORT_TYPE_CPU_MAC)
    {
        idx = gport & 0xf;
        if(MCHIP_DMPS(lchip)->cpumac_get_lport_info_by_inner_idx)
        {
            CTC_ERROR_RETURN(MCHIP_DMPS(lchip)->cpumac_get_lport_info_by_inner_idx(lchip,idx,&lport,&is_network));
        }
    }
    else
    {
        lport = SYS_MAP_SYS_LPORT_TO_DRV_LPORT(lport);
    }

    /* zero value */
    *p_value = 0;
    index = lport;
    dmps_port_info.gport = gport;

    switch (port_prop)
    {
    case CTC_PORT_PROP_NSH_SI_CHECK:
    {
        uint32 check_en_bmp[CTC_B2W_SIZE(MAX_PORT_NUM_PER_CHIP)];
        cmd = DRV_IOR(IpePortNshSiCtl_t, IpePortNshSiCtl_checkEnable_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, check_en_bmp));
        *p_value = CTC_BMP_ISSET(check_en_bmp,lport) ? 1 : 0;
        cmd = 0;
    }
        break;
    case CTC_PORT_PROP_ESID:
    if (DRV_FROM_TMM(lchip))
    {
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_mplsEvpnDestEsId_f);
    }
    else
    {
        cmd = DRV_IOR(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!CTC_IS_BIT_SET(value, 1))
        {
            return CTC_E_INVALID_CONFIG;
        }

        cmd = DRV_IOR(DsDestPort_t, DsDestPort_fcoeOuiIndex_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        *p_value = value&0xFF;
        cmd = 0;
    }
        break;
    case CTC_PORT_PROP_ESLB:
    if (DRV_FROM_TMM(lchip))
    {
        cmd = DRV_IOR(DsMplsEvpnEsLabel_t, DsMplsEvpnEsLabel_mplsEvpnEsiLabel_f);
    }
    else
    {
        cmd = DRV_IOR(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        if (!CTC_IS_BIT_SET(value, 1))
        {
            return CTC_E_INVALID_CONFIG;
        }
        *p_value = 0;
        cmd = DRV_IOR(DsPortLinkAgg_t, DsPortLinkAgg_u1_g1_channelLinkAggregate_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        *p_value |= (value&0x7F);
        cmd = DRV_IOR(DsPortLinkAgg_t, DsPortLinkAgg_channelLinkAggregateEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        *p_value |= ((value&0x1) << 0x7);
        cmd = DRV_IOR(DsPortLinkAgg_t, DsPortLinkAgg_ecid_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        *p_value |= ((value&0xFFF) << 8);
        cmd = 0;
    }
        break;
    case CTC_PORT_PROP_SELECT_MAX_SCL_PRIO_EN:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_sclPrioEn_f);
        break;
    case CTC_PORT_PROP_CLOUDSEC_EN:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_cloudSecEn_f);
        break;
    case CTC_PORT_PROP_HMAC_EN:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_hmacCheckEn_f);
        break;
    case CTC_PORT_PROP_WLAN_DECAP_WITH_RID:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_radioMacType_f);
        break;
    case CTC_PORT_PROP_DISCARD_UNENCRYPT_PKT:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_discardPlainTextPacket_f);
        break;
    case CTC_PORT_PROP_RAW_PKT_TYPE:
        ret = _sys_usw_port_get_raw_packet_type(lchip, gport, p_value);
        break;

    case CTC_PORT_PROP_VLAN_DOMAIN:
        cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_outerVlanIsCVlan_f);
        break;

    case CTC_PORT_PROP_PORT_EN:
        ret = _sys_usw_port_get_port_en(lchip, gport, p_value);
        break;

    case CTC_PORT_PROP_TRANSMIT_EN:      /**< get port whether the tranmist is enable */
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_transmitDisable_f);
        inverse_value = 1;
        break;

    case CTC_PORT_PROP_RECEIVE_EN:       /**< get port whether the receive is enable */
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_receiveDisable_f);
        inverse_value = 1;
        break;

    case CTC_PORT_PROP_BRIDGE_EN:        /**< get port whehter layer2 bridge function is enable */
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_bridgeEn_f);
        break;

    case CTC_PORT_PROP_DEFAULT_VLAN:     /**< Get default vlan id on the Port */
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_defaultVlanId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, p_value));

        return CTC_E_NONE;
        break;

    case CTC_PORT_PROP_UNTAG_PVID_TYPE:
        {
            uint32 r_value = 0;
            cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_untagDefaultVlanId_f):DRV_IOR(DsDestPort_t, DsDestPort_untagDefaultVlanId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &r_value));
            if (!r_value) /* none */
            {
                *p_value = CTC_PORT_UNTAG_PVID_TYPE_NONE;
            }
            else /* s or c */
            {
                cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_untagDefaultSvlan_f):DRV_IOR(DsDestPort_t, DsDestPort_untagDefaultSvlan_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &r_value));

                if (r_value) /* s */
                {
                    *p_value = CTC_PORT_UNTAG_PVID_TYPE_SVLAN;
                }
                else
                {
                    *p_value = CTC_PORT_UNTAG_PVID_TYPE_CVLAN;
                }
            }

            return CTC_E_NONE;

        }
        break;

    case CTC_PORT_PROP_VLAN_CTL:     /**< Get port's vlan tag control mode */
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_vlanTagCtl_f);
        break;

    case CTC_PORT_PROP_CROSS_CONNECT_EN:     /**< Get port cross connect */
        ret = _sys_usw_port_get_cross_connect(lchip, gport, p_value);
        break;

    case CTC_PORT_PROP_LEARNING_EN:     /**< Get learning enable/disable on port */
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_learningDisable_f);
        inverse_value = 1;
        break;

    case CTC_PORT_PROP_LEARN_DIS_MODE :
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_learningDisableMode_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_learningDisableMode_f);
        break;
    case CTC_PORT_PROP_FORCE_MPLS_EN:
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_openflowMplsEn_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_openflowMplsEn_f);
        break;

    case CTC_PORT_PROP_FORCE_TUNNEL_EN:
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_openflowTunnelEn_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_openflowTunnelEn_f);
        break;

    case CTC_PORT_PROP_DOT1Q_TYPE:     /**< Get port dot1q type */
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dot1QEn_f):DRV_IOR(DsDestPort_t, DsDestPort_dot1QEn_f);
        break;

    case CTC_PORT_PROP_USE_OUTER_TTL:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_useOuterTtl_f);
        break;

    case CTC_PORT_PROP_PROTOCOL_VLAN_EN:     /**< Get protocol vlan enable on port */
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_protocolVlanEn_f);
        break;

    case CTC_PORT_PROP_SRC_DISCARD_EN:     /**< set port whether the src_discard is enable */
        cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_srcDiscard_f);
        break;

    case CTC_PORT_PROP_PORT_CHECK_EN:     /**< set port whether the src port match check is enable */
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portCheckEn_f);
        break;

    /*new properties for GB*/
    case CTC_PORT_PROP_HW_LEARN_EN:     /**< hardware learning enable */
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_fastLearningEn_f);
        break;

    case CTC_PORT_PROP_SCL_IPV6_LOOKUP_EN:
        ret = CTC_E_NOT_SUPPORT;
        break;

    case CTC_PORT_PROP_SCL_IPV4_LOOKUP_EN:
        ret = CTC_E_NOT_SUPPORT;
        break;

    case CTC_PORT_PROP_SCL_USE_DEFAULT_LOOKUP:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_useDefaultVlanLookup_f);
        break;

    case CTC_PORT_PROP_SCL_FORCE_IPV6_TO_MAC:
        ret = CTC_E_NOT_SUPPORT;
        break;

    case CTC_PORT_PROP_SCL_FORCE_IPV4_TO_MAC:
        ret = CTC_E_NOT_SUPPORT;
        break;

    case CTC_PORT_PROP_TRILL_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_trillEn_f);
        break;
    case CTC_PORT_PROP_TRILL_MCAST_DECAP_EN:
        cmd = chip_is_dt2ortm ?  DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_trillMcastLoopback_f) :
                    DRV_IOR(DsPhyPortExt2_t, DsPhyPortExt2_trillMcastLoopback_f);
        break;

    case CTC_PORT_PROP_DISCARD_NON_TRIL_PKT:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_discardNonTrill_f);
        break;

    case CTC_PORT_PROP_DISCARD_TRIL_PKT:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_discardTrill_f);
        break;

    case CTC_PORT_PROP_REFLECTIVE_BRIDGE_EN:
    {
        uint32 field_val1 = 0;
        uint32 field_val2 = 0;
        *p_value = FALSE;

        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portCheckEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val1));

        cmd = DRV_IOR(DsDestPort_t, DsDestPort_reflectiveBridgeEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val2));

        *p_value = ((!field_val1) && field_val2) ? TRUE : FALSE;
        cmd = 0;
        break;
    }
    case CTC_PORT_PROP_FCOE_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_fcoeEn_f);
        break;

    case CTC_PORT_PROP_RPF_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portBasedRpfEn_f);
        break;

    case CTC_PORT_PROP_FCMAP:
        cmd = DRV_IOR(IpeIntfMapReserved_t, IpeIntfMapReserved_reserved_f);
        DRV_FIELD_IOCTL(lchip, 0, cmd, &value);
        if (CTC_IS_BIT_SET(value, 1) && DRV_IS_TSINGMA(lchip))
        {
            return CTC_E_INVALID_CONFIG;
        }
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_fcoeOuiIndex_f);
        break;

    case CTC_PORT_PROP_REPLACE_STAG_COS:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_replaceStagCos_f):DRV_IOR(DsDestPort_t, DsDestPort_replaceStagCos_f);
        break;

    case CTC_PORT_PROP_REPLACE_CTAG_COS:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_replaceCtagCos_f):DRV_IOR(DsDestPort_t, DsDestPort_replaceCtagCos_f);
        break;

    case CTC_PORT_PROP_REPLACE_STAG_TPID:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_replaceStagTpid_f):DRV_IOR(DsDestPort_t, DsDestPort_replaceStagTpid_f);
        break;

    case CTC_PORT_PROP_REPLACE_DSCP_EN:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dscpRemarkMode_f):DRV_IOR(DsDestPort_t, DsDestPort_dscpRemarkMode_f);
        DRV_FIELD_IOCTL(lchip, lport, cmd, &value);
        if(value == 2)
        {
            *p_value = 1;
        }
        cmd = 0;
        break;

    case CTC_PORT_PROP_L3PDU_ARP_ACTION:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_arpExceptionType_f);
        break;

    case CTC_PORT_PROP_L3PDU_DHCP_ACTION:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_dhcpV4ExceptionType_f);
        break;

    case CTC_PORT_PROP_L3PDU_DHCP_V6_ACTION:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_dhcpV6ExceptionType_f);
        break;

    case CTC_PORT_PROP_TUNNEL_RPF_CHECK:
        cmd = chip_is_dt2ortm ? DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_tunnelRpfCheck_f) :
        DRV_IOR(DsPhyPortExt2_t, DsPhyPortExt2_tunnelRpfCheck_f);
        break;

    case CTC_PORT_PROP_PTP_EN:
        if (!(SYS_DMPS_NETWORK_PORT == sys_usw_is_network_port(lchip, gport)))
        {
            return CTC_E_INVALID_PORT;
        }
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_ptpIndex_f);
        break;

    case CTC_PORT_PROP_PTP_DOMAIN_ID:
        if (!DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_todRtcId_f);
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, p_value));
        *p_value = *p_value? 1 : 0;
        cmd = 0;
        break;

    case CTC_PORT_PROP_RPF_TYPE:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_rpfType_f);
        break;

    case CTC_PORT_PROP_IS_LEAF:
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_isLeaf_f);
        break;

    case CTC_PORT_PROP_PKT_TAG_HIGH_PRIORITY:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_ingressTagHighPriority_f);
        break;

    case CTC_PORT_PROP_ROUTE_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_routeDisable_f);
        inverse_value = 1;
        break;

    case CTC_PORT_PROP_PRIORITY_TAG_EN:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_priorityTagEn_f):DRV_IOR(DsDestPort_t, DsDestPort_priorityTagEn_f);
        break;

    case CTC_PORT_PROP_IPG:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_ipgIndex_f);
        break;

    case CTC_PORT_PROP_DEFAULT_PCP:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_defaultPcp_f):DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_defaultPcp_f);
        break;

    case CTC_PORT_PROP_DEFAULT_DEI:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_defaultDei_f):DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_defaultDei_f);
        break;

    case CTC_PORT_PROP_NVGRE_MCAST_NO_DECAP:
        cmd = chip_is_dt2ortm ? DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_nvgreMcastLoopbackMode_f) :
        DRV_IOR(DsPhyPortExt2_t, DsPhyPortExt2_nvgreMcastLoopbackMode_f);
        break;

    case CTC_PORT_PROP_VXLAN_MCAST_NO_DECAP:
        cmd = chip_is_dt2ortm ?  DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_vxlanMcastLoopbackMode_f) :
        DRV_IOR(DsPhyPortExt2_t, DsPhyPortExt2_vxlanMcastLoopbackMode_f);
        break;

    case CTC_PORT_PROP_IP_TUNNEL_MCAST_NO_DECAP:
        cmd =  chip_is_dt2ortm ? DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_mcastVpnLoopback_f) :
        DRV_IOR(DsPhyPortExt2_t, DsPhyPortExt2_mcastVpnLoopback_f);
        inverse_value = 1;
        break;
    case CTC_PORT_PROP_QOS_POLICY:
        CTC_ERROR_RETURN(_sys_usw_port_unmap_qos_policy(lchip, lport, p_value));
        cmd = 0;
        break;

    case CTC_PORT_PROP_SCL_HASH_FIELD_SEL_ID:
        cmd = chip_is_dt2ortm ? DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_sclFlowHashFieldSel_f) :
        DRV_IOR(DsPhyPortExt2_t, DsPhyPortExt2_sclFlowHashFieldSel_f);
        break;

    case CTC_PORT_PROP_SNOOPING_PARSER:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_forceSecondParser_f);
        break;

    case CTC_PORT_PROP_FLOW_LKUP_BY_OUTER_HEAD:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_aclQosUseOuterInfo_f);
        break;
    case CTC_PORT_PROP_IPFIX_LKUP_BY_OUTER_HEAD:
        cmd = DRV_FROM_TMM(lchip) ? DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_ipfixUseOuterInfo_f) :
                DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_ipfixAndMicroflowUseOuterInfo_f);
        break;
    case CTC_PORT_PROP_AWARE_TUNNEL_INFO_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_aclKeyMergeInnerAndOuterHdr_f);
        break;

    case CTC_PORT_PROP_IPFIX_AWARE_TUNNEL_INFO_EN:
        cmd = chip_is_dt2ortm ?  DRV_IOR(DsSrcPort_t, DsSrcPort_ipfixAndMicroflowMergeHdr_f) :
        DRV_IOR(DsSrcPort_t, DsSrcPort_ipfixMergeHdr_f);
        break;

    case CTC_PORT_PROP_NVGRE_ENABLE:
        if (DRV_FROM_TMM(lchip))
        {
            cmd = DRV_IOR(DsPhyPortExt2_t, DsPhyPortExt2_nvgreEnable_f);
        }
        else
        {
            cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_nvgreEnable_f);
        }
        break;
    case CTC_PORT_PROP_LOGIC_PORT_CHECK_EN:
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_logicPortCheckEn_f);
        break;
    case CTC_PORT_PROP_METADATA_OVERWRITE_PORT:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_0_aclUseGlobalPortType_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,lport, cmd, p_value));
        if(*p_value == 3)
        {
            *p_value = 1;
        }
        else
        {
            *p_value = 0;
        }
        cmd = 0;
        break;
    case CTC_PORT_PROP_METADATA_OVERWRITE_UDF:
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " API or some feature is not supported \n");
        return CTC_E_NOT_SUPPORT;

        break;
    case CTC_PORT_PROP_SRC_MISMATCH_EXCEPTION_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_srcMismatchExceptionEn_f);
        break;

    case CTC_PORT_PROP_STATION_MOVE_PRIORITY:
    case CTC_PORT_PROP_STATION_MOVE_ACTION:
        CTC_ERROR_RETURN(sys_usw_l2_get_station_move(lchip, gport, port_prop, p_value));
        if((port_prop == CTC_PORT_PROP_STATION_MOVE_ACTION) && (sys_usw_chip_is_local(lchip, gchip)) && (*p_value == CTC_PORT_STATION_MOVE_ACTION_TYPE_DISCARD))
        {
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_srcMismatchExceptionEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, CTC_MAP_GPORT_TO_LPORT(gport), cmd, p_value));
            *p_value = *p_value ? CTC_PORT_STATION_MOVE_ACTION_TYPE_DISCARD_TOCPU : CTC_PORT_STATION_MOVE_ACTION_TYPE_DISCARD;
        }
        cmd = 0;
        break;

    case CTC_PORT_PROP_EFD_EN:
        if(!DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(IpePortEfdCtl_t, IpePortEfdCtl_array_0_efdEnable_f+(lport&0xFF));
            ret = DRV_FIELD_IOCTL(lchip, (lport>>8), cmd, p_value);
        }
        else
        {
            cmd = DRV_IOR(IpePortEfdCtl_t, DRV_ENTRY_FLAG);/*AT*/
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, (lport>>9), cmd, &port_efd_ctl));
            GetIpePortEfdCtl(A, portEfdEnable_f, &port_efd_ctl, efd_en);
            *p_value = (CTC_BMP_ISSET(efd_en, lport))?1:0;
        }
        cmd = 0;
        break;

    case CTC_PORT_PROP_ADD_DEFAULT_VLAN_DIS:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_addDefaultVlanDisable_f);
        break;

    case CTC_PORT_PROP_LOGIC_PORT:
         cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_defaultLogicSrcPort_f);
         break;

     case CTC_PORT_PROP_GPORT:
        if(CTC_IS_CPU_PORT(gport))
        {
            *p_value = gport;
        }
        else
        {
            ret = sys_usw_port_get_global_port(lchip, lport, &value);
            if (CTC_E_NONE == ret)
            {
                *p_value = value;
            }
        }
        break;

    case CTC_PORT_PROP_APS_FAILOVER_EN:
        if (DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        ret = _sys_usw_port_get_aps_failover_en(lchip, gport, p_value);
        break;

    case CTC_PORT_PROP_LINKAGG_FAILOVER_EN:
        ret = _sys_usw_port_get_linkagg_failover_en(lchip, gport, p_value);
        break;

    case CTC_PORT_PROP_APS_SELECT_GRP_ID:
        ret = _sys_usw_port_get_aps_select_grp_id(lchip, gport, p_value);
        break;

    case CTC_PORT_PROP_APS_SELECT_WORKING:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_apsSelectProtectingPath_f);
        inverse_value = 1;
        break;
    case CTC_PORT_PROP_CID:
        {
            uint8 station_move_mode = 0;
            sys_usw_global_get_station_move_mode(lchip, &station_move_mode);
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_categoryId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, p_value));
            if (station_move_mode)
            {
                *p_value &=0xFFF;
            }
            cmd =0;
        }
        break;
    case CTC_PORT_PROP_TX_CID_HDR_EN:
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_withCidHeader_f);
        break;
    case CTC_PORT_PROP_WLAN_PORT_TYPE:
        ret = _sys_usw_port_get_wlan_port_type(lchip, gport, p_value);
        break;
    case CTC_PORT_PROP_WLAN_PORT_ROUTE_EN:
        if (DRV_FROM_TMM(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        ret = _sys_usw_port_get_wlan_port_route(lchip, gport, p_value);
        break;
    case CTC_PORT_PROP_DSCP_SELECT_MODE:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dscpRemarkMode_f):DRV_IOR(DsDestPort_t, DsDestPort_dscpRemarkMode_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, p_value));
        cmd = 0;
        break;
    case CTC_PORT_PROP_DEFAULT_DSCP:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_defaultDscp_f):DRV_IOR(DsDestPort_t, DsDestPort_defaultDscp_f);
        break;
    case CTC_PORT_PROP_REPLACE_PCP_DEI:
        cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_replacePortPcp_f):DRV_IOR(DsDestPort_t, DsDestPort_replacePortPcp_f);
        break;
    case CTC_PORT_PROP_CUT_THROUGH_EN:
        _sys_usw_port_get_cut_through_en(lchip,gport,p_value);
        cmd = 0;
        break;

    case CTC_PORT_PROP_SD_ACTION:
        ret = _sys_usw_port_get_sd_action(lchip, CTC_INGRESS, index, p_value);
        cmd = 0;
        break;

    case CTC_PORT_PROP_LOOP_WITH_SRC_PORT:
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_sourcePortToHeader_f);
        break;

    case CTC_PORT_PROP_LB_HASH_ECMP_PROFILE:
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_portBasedHashProfileId0_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portBasedHashProfileId0_f);
        break;

    case CTC_PORT_PROP_LB_HASH_LAG_PROFILE:
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_portBasedHashProfileId1_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portBasedHashProfileId1_f);
        break;
    case CTC_PORT_PROP_LB_HASH_PROFILE:
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_portBasedHashProfileId0_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portBasedHashProfileId0_f);
        break;
    case CTC_PORT_PROP_DENY_LEARNING :
        if (!DRV_FLD_IS_EXISIT(DsSrcPort_t, DsSrcPort_denyLearning_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_denyLearning_f);
        break;
    case CTC_PORT_PROP_UDF_CLASSID:
        if (!DRV_FLD_IS_EXISIT(DsPhyPort_t, DsPhyPort_udfLabel_f))
        {
            return CTC_E_NOT_SUPPORT;
        }
        cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_udfLabel_f);
        break;

    case CTC_PORT_PROP_XPIPE_EN:
        *p_value = p_usw_port_master[lchip]->port_prop[lport].xpipe_type;
        cmd = 0;
        break;
     case CTC_PORT_PROP_XPIPE_MODE:
        SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
        CTC_ERROR_RETURN(_sys_usw_port_get_xpipe_mode(lchip, gport, p_value));
        cmd = 0;
        break;
     case CTC_PORT_PROP_FAST_PFC_EN:
         SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
         CTC_ERROR_RETURN(_sys_usw_port_get_fpfc_en(lchip, gport, p_value));
         break;
     case CTC_PORT_PROP_QOS_WRR_EN:
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &index));
        if (!SYS_IS_NETWORK_CHANNEL(index))
        {
            return CTC_E_INVALID_PARAM;
        }
        if (SYS_CB_PTR(SYS_CB_QOS_WRR_EN))
        {
            ret = SYS_CB(SYS_CB_QOS_WRR_EN, lchip, gport, p_value, FALSE);
        }
        else
        {
            cmd = DRV_IOR(DsQMgrNetSchPpsCfg_t, DsQMgrNetSchPpsCfg_ppsMode_f);
        }
        break;
    case CTC_PORT_PROP_INBAND_CPU_TRAFFIC_EN:
        return CTC_E_NOT_SUPPORT;
    case CTC_PORT_PROP_MUX_TYPE:
        ret = _sys_usw_port_get_mux_type(lchip, gport, p_value);
        break;
    case CTC_PORT_PROP_STK_GRP_ID:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_cFlexFwdSgGroupSel_f);
        break;
    case CTC_PORT_PROP_LB_HASH_VALUE:
        if(DRV_FROM_AT(lchip))
        {
            cmd = DRV_IOR(IpeFwdIngressPortLbnCtl_t, (IpeFwdIngressPortLbnCtl_gPort_0_lbn_f + (lport & 0x7)));
            ret = DRV_FIELD_IOCTL(lchip, (lport>>3), cmd, p_value);
        }
        else
        {
            cmd = DRV_IOR(IpeFwdIngressPortLbnCtl_t, IpeFwdIngressPortLbnCtl_gPort_0_lbn_f + lport);
            ret = DRV_FIELD_IOCTL(lchip, 0, cmd, p_value);
        }
        cmd = 0;
        break;
    case CTC_PORT_PROP_SFD_EN:
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
        if ((SYS_DMPS_NETWORK_PORT != port_type) && (SYS_DMPS_CPU_MAC_PORT != port_type) &&
            (SYS_DMPS_CPUMAC_NETWORK_PORT != port_type))
        {
            return CTC_E_INVALID_PORT;
        }
        ret = sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SFD_ENABLE, (void*)p_value);
        *p_value = (*p_value)?0:1;
        break;

    case CTC_PORT_PROP_MAX_FRAME_SIZE:
    case CTC_PORT_PROP_MIN_FRAME_SIZE:
        if(MCHIP_PORT(lchip)->port_get_property)
        {
            ret = MCHIP_PORT(lchip)->port_get_property(lchip, gport, port_prop, p_value);
        }
        else
        {
            return CTC_E_INVALID_PTR;
        }
        break;
    case CTC_PORT_PROP_PP_ID:
        {
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &value));
            *p_value = value;
        }
        break;
    case CTC_PORT_PROP_OBM_DSCP_DOMAIN:
    case CTC_PORT_PROP_OBM_COS_DOMAIN:
    case CTC_PORT_PROP_OBM_DEFAULT_PCP:
        CTC_ERROR_RETURN(_sys_usw_port_get_obm_domain(lchip, port_prop, gport, lport, p_value));
        break;
    case CTC_PORT_PROP_OBM_POLICY:
        CTC_ERROR_RETURN(_sys_usw_port_unmap_obm_policy(lchip, gport, lport, p_value));
        break;
    case CTC_PORT_PROP_TRUNCATION_EN:
        {
            uint32 port_type;
            uint32 truncate_bitmap[8];
            EpeHeaderEditTruncationCtl_m truncationctl;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, &port_type));
            if(port_type != SYS_DMPS_NETWORK_PORT && port_type != SYS_DMPS_DMA_PORT && port_type != SYS_DMPS_OAM_PORT && port_type != SYS_DMPS_CPU_MAC_PORT && port_type != SYS_DMPS_CPUMAC_NETWORK_PORT)
            {
                return CTC_E_INVALID_PORT;
            }
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &index));
            cmd = DRV_IOR(EpeHeaderEditTruncationCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &truncationctl));
            GetEpeHeaderEditTruncationCtl(A, cfgTruncationEn_f, &truncationctl, truncate_bitmap);
            *p_value = ((CTC_BMP_ISSET(truncate_bitmap, index)>>index)&1);
            cmd = 0;
        }
        break;
    default:
        return CTC_E_NOT_SUPPORT;
    }

    if (ret != CTC_E_NONE)
    {
        return ret;
    }

    if (cmd == 0)
    {
        /*when cmd == 0, get value from  software memory*/
        return CTC_E_NONE;
    }

    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, p_value));

    *p_value = inverse_value ? (!(*p_value)) : (*p_value);


    return CTC_E_NONE;
}


int32
_sys_usw_port_set_mlag_isolation(uint8 lchip, ctc_port_isolation_t* p_port_isolation)
{
    uint16 lport = 0;
    uint32 drv_port = 0;
    uint32 cmd = 0;
    uint8 loop = 0;
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    if (!CTC_IS_LINKAGG_PORT(p_port_isolation->gport))
    {
         SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_port_isolation->gport, lchip, lport);
    }
    else if (MCHIP_CAP(SYS_CAP_LINKAGG_GROUP_NUM) <= CTC_MAP_GPORT_TO_LPORT(p_port_isolation->gport))
    {
         SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid parameter \n");
         return CTC_E_INVALID_PARAM;
    }
    /*mlag port isolation*/
    if (!(p_port_isolation->is_linkagg))
    {
        /* TMM cannot find lag group in metfifo, need padding lag member */
         drv_port = SYS_MAP_CTC_GPORT_TO_DRV_GPORT(p_port_isolation->gport);
         cmd = DRV_IOW(MetFifoIsolateCtl_t, MetFifoIsolateCtl_peerLinkSourcePort1_f);
         CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &drv_port));
         for (loop = 0; loop < (SYS_USW_MAX_PORT_NUM_PER_CHIP / BITS_NUM_OF_WORD); loop++)
         {
             p_port_isolation->pbm[loop] = ~(p_port_isolation->pbm[loop]);
         }
         p_port_isolation->pbm[loop-1] = (p_port_isolation->pbm[loop-1] | SYS_CAP_PORT_MISC_PORT_MASK);
         cmd = DRV_IOW(MetFifoIsolateCtl_t, MetFifoIsolateCtl_portNonBlockBitmap1_f);
         CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &p_port_isolation->pbm));

    }
    /*mlag linkagg isolation*/
    else
    {
        if (DRV_FROM_TMM(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        drv_port = SYS_MAP_CTC_GPORT_TO_DRV_GPORT(p_port_isolation->gport);
        cmd = DRV_IOW(MetFifoIsolateCtl_t, MetFifoIsolateCtl_peerLinkSourcePort1_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &drv_port));
        for (loop = 0; loop < 2; loop++)
        {
           p_port_isolation->pbm[loop] = ~(p_port_isolation->pbm[loop]);
        }
         cmd = DRV_IOW(MetFifoIsolateCtl_t, MetFifoIsolateCtl_lagNonBlockBitmap1_f);
         CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &p_port_isolation->pbm));
    }
    return CTC_E_NONE;
}


int32
_sys_usw_port_get_mlag_isolation(uint8 lchip, ctc_port_isolation_t* p_port_isolation)
{
    uint32 drv_port = 0;
    uint32 cmd = 0;
    uint8 loop = 0;
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    cmd = DRV_IOR(MetFifoIsolateCtl_t, MetFifoIsolateCtl_peerLinkSourcePort1_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &drv_port));
    p_port_isolation->gport = SYS_MAP_DRV_GPORT_TO_CTC_GPORT(drv_port);

    if (!(p_port_isolation->is_linkagg))
    {
        cmd = DRV_IOR(MetFifoIsolateCtl_t, MetFifoIsolateCtl_portNonBlockBitmap1_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &p_port_isolation->pbm));
        for (loop = 0; loop < (SYS_USW_MAX_PORT_NUM_PER_CHIP / BITS_NUM_OF_WORD); loop++)
        {
            p_port_isolation->pbm[loop] = ~(p_port_isolation->pbm[loop]);
        }
    }
    else
    {
        cmd = DRV_IOR(MetFifoIsolateCtl_t, MetFifoIsolateCtl_lagNonBlockBitmap1_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &p_port_isolation->pbm));
        for (loop = 0; loop < 2; loop++)
        {
            p_port_isolation->pbm[loop] = ~(p_port_isolation->pbm[loop]);
        }
    }
    return CTC_E_NONE;
}

int32
_sys_usw_port_check_restriction_mode(uint8 lchip, uint32 gport, ctc_port_restriction_t* p_restriction)
{
    uint32 cmd = 0;
    uint32 value = 0;
    uint16 lport = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property, gport:0x%04X\n", gport);

    /*Sanity check*/
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    p_restriction->mode = CTC_PORT_RESTRICTION_DISABLE;

    if (CTC_INGRESS == p_restriction->dir)
    {
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        value = (value & 0x1F) | ((value >> 1) & 0x20);
    }
    else if (CTC_EGRESS == p_restriction->dir)
    {
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_destPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    if (0 != value)
    {
        if (0x30 == (value & 0x38))
        {
            p_restriction->mode = CTC_PORT_RESTRICTION_PVLAN;
            p_restriction->type = CTC_PORT_PVLAN_PROMISCUOUS;
        }
        else if  (0x38 == (value & 0x38))
        {
            p_restriction->mode = CTC_PORT_RESTRICTION_PVLAN;
            p_restriction->type = CTC_PORT_PVLAN_ISOLATED;
        }
        else if (0x20 == (value & 0x30))
        {
            p_restriction->mode = CTC_PORT_RESTRICTION_PVLAN;
            p_restriction->type = CTC_PORT_PVLAN_COMMUNITY;
            p_restriction->isolated_id = value & (~((uint32)0x30));
        }
        else
        {
            p_restriction->mode = CTC_PORT_RESTRICTION_PORT_ISOLATION;

            if (CTC_INGRESS == p_restriction->dir)
            {
                p_restriction->isolated_id = value;
            }
            else if (CTC_EGRESS == p_restriction->dir)
            {
                p_restriction->isolated_id = value;
            }
        }
    }
    return CTC_E_NONE;
}

int32
sys_usw_port_set_restriction(uint8 lchip, uint32 gport, ctc_port_restriction_t* p_restriction)
{
    int32  ret = CTC_E_NONE;

    uint16 lport = 0;
    uint32 value = 0;
    uint32 value_igs = 0;
    uint32 cmd = 0;
    ctc_port_restriction_t restriction;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property, gport:0x%04X, mode:%d, isolated_id:%d, dir:%d\n", \
                     gport, p_restriction->mode, p_restriction->isolated_id, p_restriction->dir);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    sal_memset(&restriction, 0, sizeof(ctc_port_restriction_t));

    restriction.dir = CTC_INGRESS;
    CTC_ERROR_RETURN(_sys_usw_port_check_restriction_mode(lchip, gport, &restriction));
    if (((CTC_PORT_RESTRICTION_PVLAN == restriction.mode) && (CTC_PORT_RESTRICTION_PORT_ISOLATION == p_restriction->mode))
       || ((CTC_PORT_RESTRICTION_PORT_ISOLATION == restriction.mode) && (CTC_PORT_RESTRICTION_PVLAN == p_restriction->mode)))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " port has another restriction feature \n");
        return CTC_E_INVALID_CONFIG;
    }

    restriction.dir = CTC_EGRESS;
    CTC_ERROR_RETURN(_sys_usw_port_check_restriction_mode(lchip, gport, &restriction));
    if (((CTC_PORT_RESTRICTION_PVLAN == restriction.mode) && (CTC_PORT_RESTRICTION_PORT_ISOLATION == p_restriction->mode))
       || ((CTC_PORT_RESTRICTION_PORT_ISOLATION == restriction.mode) && (CTC_PORT_RESTRICTION_PVLAN == p_restriction->mode)))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " port has another restriction feature \n");
        return CTC_E_INVALID_CONFIG;
    }

    switch (p_restriction->mode)
    {
    case CTC_PORT_RESTRICTION_PVLAN:

        if (CTC_PORT_PVLAN_PROMISCUOUS == p_restriction->type)
        {
            /* port_isolate_id[5:0] = 6'b110XXX */
            value_igs = 0x50;
            value = 0x30;
        }
        else if (CTC_PORT_PVLAN_ISOLATED == p_restriction->type)
        {
            /* port_isolate_id[5:0] = 6'b111XXX */
            value_igs = 0x58;
            value = 0x38;
        }
        else if (CTC_PORT_PVLAN_COMMUNITY == p_restriction->type)
        {
            value = p_restriction->isolated_id;
            CTC_MAX_VALUE_CHECK(value, MCHIP_CAP(SYS_CAP_PVLAN_COMMUNITY_ID_NUM));
            /* port_isolate_id[5:0] = 6'b10XXXX */
            value_igs = (value | 0x40);
            value = (value | 0x20);
        }
        else if (CTC_PORT_PVLAN_NONE == p_restriction->type)
        {
            value_igs = 0;
            value = 0;
        }
        else
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid parameter \n");
            return CTC_E_INVALID_PARAM;
        }
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value_igs));

        cmd = DRV_IOW(DsDestPort_t, DsDestPort_destPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        break;

    case CTC_PORT_RESTRICTION_PORT_ISOLATION:
        CTC_MAX_VALUE_CHECK(p_restriction->isolated_id, (SYS_USW_ISOLATION_GROUP_NUM - 1));
        CTC_MAX_VALUE_CHECK(p_restriction->type, CTC_PORT_ISOLATION_ALL + CTC_PORT_ISOLATION_UNKNOW_UCAST\
                                                 + CTC_PORT_ISOLATION_UNKNOW_MCAST + CTC_PORT_ISOLATION_KNOW_UCAST\
                                                 + CTC_PORT_ISOLATION_KNOW_MCAST + CTC_PORT_ISOLATION_BCAST);
        if (0 == p_usw_port_master[lchip]->use_isolation_id)
        {
              SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " port has another restriction feature \n");
              return CTC_E_INVALID_CONFIG;

        }
        if ((CTC_INGRESS == p_restriction->dir) || (CTC_BOTH_DIRECTION == p_restriction->dir))
        {
            value = p_restriction->isolated_id;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        }
        if ((CTC_EGRESS == p_restriction->dir) || (CTC_BOTH_DIRECTION == p_restriction->dir))
        {
            value = p_restriction->isolated_id;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_destPortIsolateId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        }

        break;

    case CTC_PORT_RESTRICTION_PORT_BLOCKING:
        CTC_MAX_VALUE_CHECK(p_restriction->type, CTC_PORT_BLOCKING_UNKNOW_UCAST\
                                                 + CTC_PORT_BLOCKING_UNKNOW_MCAST + CTC_PORT_BLOCKING_KNOW_UCAST\
                                                 + CTC_PORT_BLOCKING_KNOW_MCAST + CTC_PORT_BLOCKING_BCAST);
        CTC_ERROR_RETURN(_sys_usw_port_set_port_blocking(lchip, gport, p_restriction->type));
        break;

    case CTC_PORT_RESTRICTION_DISABLE:
        value = 0;
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_destPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));

        CTC_ERROR_RETURN(_sys_usw_port_set_port_blocking(lchip, gport, 0));
        break;

    default:
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid parameter \n");
        return CTC_E_INVALID_PARAM;
    }
    return ret;
}

int32
sys_usw_port_get_restriction(uint8 lchip, uint32 gport, ctc_port_restriction_t* p_restriction)
{
    uint16 lport = 0;
    uint32 value = 0;
    uint32 cmd = 0;
    uint16 block_type = 0;
    ctc_port_restriction_t restriction;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property, gport:0x%04X\n", gport);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    sal_memset(&restriction, 0, sizeof(ctc_port_restriction_t));

    restriction.dir = CTC_INGRESS;
    CTC_ERROR_RETURN(_sys_usw_port_check_restriction_mode(lchip, gport, &restriction));
    if (((CTC_PORT_RESTRICTION_PVLAN == restriction.mode) && (CTC_PORT_RESTRICTION_PORT_ISOLATION == p_restriction->mode)))
    {
        p_restriction->isolated_id = 0;
        return CTC_E_NONE;
    }
    else if (((CTC_PORT_RESTRICTION_PORT_ISOLATION == restriction.mode) && (CTC_PORT_RESTRICTION_PVLAN == p_restriction->mode)))
    {
        p_restriction->type = CTC_PORT_PVLAN_NONE;
        return CTC_E_NONE;
    }

    restriction.dir = CTC_EGRESS;
    CTC_ERROR_RETURN(_sys_usw_port_check_restriction_mode(lchip, gport, &restriction));
    if (((CTC_PORT_RESTRICTION_PVLAN == restriction.mode) && (CTC_PORT_RESTRICTION_PORT_ISOLATION == p_restriction->mode)))
    {
        p_restriction->isolated_id = 0;
        return CTC_E_NONE;
    }
    else if (((CTC_PORT_RESTRICTION_PORT_ISOLATION == restriction.mode) && (CTC_PORT_RESTRICTION_PVLAN == p_restriction->mode)))
    {
        p_restriction->type = CTC_PORT_PVLAN_NONE;
        return CTC_E_NONE;
    }

    if (CTC_INGRESS == p_restriction->dir)
    {
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        value = (value & 0x1F) | ((value >> 1) & 0x20);
    }
    else if (CTC_EGRESS == p_restriction->dir)
    {
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_destPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    switch (p_restriction->mode)
    {
        case CTC_PORT_RESTRICTION_DISABLE:
            break;
        case CTC_PORT_RESTRICTION_PVLAN:
            if (0x30 == (value & 0x38))
            {
                p_restriction->type = CTC_PORT_PVLAN_PROMISCUOUS;
            }
            else if  (0x38 == (value & 0x38))
            {
                p_restriction->type = CTC_PORT_PVLAN_ISOLATED;
            }
            else if (0x20 == (value & 0x30))
            {
                p_restriction->type = CTC_PORT_PVLAN_COMMUNITY;
                p_restriction->isolated_id = value & (~((uint32)0x30));
            }
            break;
        case CTC_PORT_RESTRICTION_PORT_BLOCKING:
            CTC_ERROR_RETURN(_sys_usw_port_get_port_blocking(lchip, gport, &block_type));
            if (0 != block_type)
            {
                p_restriction->type = block_type;
            }
            break;
        case CTC_PORT_RESTRICTION_PORT_ISOLATION:
            if (0 == p_usw_port_master[lchip]->use_isolation_id)
            {
                  SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " port has another restriction feature \n");
                  return CTC_E_INVALID_CONFIG;
            }

            if (CTC_INGRESS == p_restriction->dir)
            {
                p_restriction->isolated_id = value;
            }
            else if (CTC_EGRESS == p_restriction->dir)
            {
                p_restriction->isolated_id = value;
            }
            break;
        default:
            return CTC_E_INVALID_PARAM;
    }
    return CTC_E_NONE;
}

int32
_sys_usw_port_set_isolation_id(uint8 lchip, ctc_port_isolation_t* p_port_isolation)
{
    uint32 igs_isolation_id = 0;
    uint32 igs_isolation_id_tmp = 0;
    uint32 igs_isolation_bitmap[2];
    uint16 lport = 0;
    uint16 loop = 0;
    uint16 entry_num = 0;
    uint32 cmd = 0;
    uint32 tbl_id = DRV_FROM_AT(lchip) ? DsUcQWritePortBlockMask_t : DsPortBlockMask_t;
    uint8 isolation_group = 0;
    DsPortBlockMask_m ds_port_blockmask;

    /***************************************
     Ingress isolation resource
     ***************************************/
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    if (0 == p_port_isolation->mode)
    {
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_port_isolation->gport, lchip, lport);
    }

    sal_memset(&ds_port_blockmask, 0, sizeof(DsPortBlockMask_m));
    sal_memcpy(igs_isolation_bitmap, p_usw_port_master[lchip]->igs_isloation_bitmap, sizeof(p_usw_port_master[lchip]->igs_isloation_bitmap));
    cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &igs_isolation_id));

    if(DRV_FROM_TMM(lchip)) /* TMM: Isolation group num is 64, Max Member is 256 */
    {
         entry_num = MCHIP_CAP(SYS_CAP_ISOLATION_PER_GROUP_ENTRY_NUM);
    }
    else
    {
        switch (p_usw_port_master[lchip]->isolation_group_mode)
        {
             case CTC_ISOLATION_GROUP_MODE_64:
                 entry_num = 2;
                 break;
             case CTC_ISOLATION_GROUP_MODE_32:
                 entry_num = 4;
                 break;
             case CTC_ISOLATION_GROUP_MODE_16:
                 entry_num = 8;
                 break;
             default:
                SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid parameter \n");
                return CTC_E_INVALID_PARAM;
         }
    }

    if ((0 == igs_isolation_id) && (0 == p_port_isolation->mode))
    {
        uint8 bit = 0;
        for (loop = 0; loop < entry_num; loop++)
        {
            if (0 != p_port_isolation->pbm[loop])
            {
                break;
            }
            if (entry_num == (loop + 1))
            {
                return CTC_E_NONE;
            }
        }
        for (bit = 1; bit < SYS_USW_ISOLATION_ID_NUM; bit++)
        {
            if (!CTC_IS_BIT_SET(igs_isolation_bitmap[bit/32], bit%32))
            {
                igs_isolation_id = bit;
                break;
            }
        }
        if (SYS_USW_ISOLATION_ID_NUM == bit)
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No resource in ASIC \n");
            return CTC_E_NO_RESOURCE;

        }

        CTC_BIT_SET(igs_isolation_bitmap[bit/32], bit%32);

        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "src-port: %d, igs_isolation_bitmap0: 0x%x,  igs_isolation_bitmap1: 0x%x,igs_isolation_id:%d, allocate\n",
                         lport, igs_isolation_bitmap[0], igs_isolation_bitmap[1],igs_isolation_id);
         cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
         CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &igs_isolation_id));

    }
    else if (0 == p_port_isolation->mode)
    {
        for (loop = 0; loop < entry_num; loop++)
        {
             if (0 != p_port_isolation->pbm[loop])
             {
                 break;
             }
        }

        /*clear isolation, recycle resource */
        if (entry_num == loop)
        {
            CTC_BIT_UNSET(igs_isolation_bitmap[igs_isolation_id/32], igs_isolation_id%32);
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &igs_isolation_id_tmp));
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "recycle the old isolation id:%d, src-port: %d, igs_isolation_bitmap0: 0x%x,igs_isolation_bitmap1: 0x%x\n",
                         igs_isolation_id, lport, igs_isolation_bitmap[0],igs_isolation_bitmap[1]);
        }else
        {
             SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "src-port: %d, igs_isolation_bitmap: 0x%x, igs_isolation_bitmap1: 0x%x,igs_isolation_id:%d, Update\n",
                         lport, igs_isolation_bitmap[0],igs_isolation_bitmap[1], igs_isolation_id);
        }
    }
    else
    {
        igs_isolation_id = p_port_isolation->gport;
        CTC_MAX_VALUE_CHECK(igs_isolation_id, (SYS_USW_ISOLATION_GROUP_NUM - 1));
    }

    for (loop = 0; loop < entry_num; loop++)
    {
         isolation_group = igs_isolation_id * entry_num + loop;
         SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "isolation_group: %d\n", isolation_group);
         cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
         CTC_ERROR_RETURN(DRV_IOCTL(lchip, isolation_group, cmd, &ds_port_blockmask));
         if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_UNKNOW_UCAST))
         {
            SetDsPortBlockMask(A, array_0_blockMask_f, &ds_port_blockmask, &p_port_isolation->pbm[loop]);
         }
         if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_UNKNOW_MCAST))
         {
            SetDsPortBlockMask(A, array_1_blockMask_f, &ds_port_blockmask, &p_port_isolation->pbm[loop]);
         }
         if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_KNOW_UCAST))
         {
            SetDsPortBlockMask(A, array_2_blockMask_f, &ds_port_blockmask, &p_port_isolation->pbm[loop]);
         }
         if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_KNOW_MCAST))
         {
            SetDsPortBlockMask(A, array_3_blockMask_f, &ds_port_blockmask, &p_port_isolation->pbm[loop]);
         }
         if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_BCAST))
         {
            SetDsPortBlockMask(A, array_4_blockMask_f, &ds_port_blockmask, &p_port_isolation->pbm[loop]);
         }
         cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
         CTC_ERROR_RETURN(DRV_IOCTL(lchip, isolation_group, cmd, &ds_port_blockmask));
         cmd = DRV_IOW(DsMcQWritePortBlockMask_t, DRV_ENTRY_FLAG);
         CTC_ERROR_RETURN(DRV_IOCTL(lchip, isolation_group, cmd, &ds_port_blockmask));
     }

    sal_memcpy(p_usw_port_master[lchip]->igs_isloation_bitmap, igs_isolation_bitmap, sizeof(p_usw_port_master[lchip]->igs_isloation_bitmap));
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_MASTER, 1);

    return CTC_E_NONE;
}

int32
sys_usw_port_set_isolation_mode(uint8 lchip, uint8 choice_mode)
{
    if (0 == choice_mode)
    {
        p_usw_port_master[lchip]->use_isolation_id = 0;
    }
    else if (1 == choice_mode)
    {
        p_usw_port_master[lchip]->use_isolation_id = 1;
    }
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_MASTER, 1);
    return CTC_E_NONE;
}

int32
sys_usw_port_get_isolation_mode(uint8 lchip, uint8* p_choice_mode)
{
    *p_choice_mode = p_usw_port_master[lchip]->use_isolation_id;
    return CTC_E_NONE;
}

int32
sys_usw_port_set_isolation(uint8 lchip, ctc_port_isolation_t* p_port_isolation)
{
    uint32 cmd = 0;
    uint32 isolation_group = 0;
    uint32 pbm = 0;
    uint32 igs_isolation_id = 0;
    uint16 lport = 0;
    DsPortIsolation_m ds_port_isolation;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    if (p_port_isolation->mlag_en)
    {
        if (p_port_isolation->use_isolation_id)
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid parameter \n");
            return CTC_E_INVALID_PARAM;
        }
        CTC_ERROR_RETURN(_sys_usw_port_set_mlag_isolation(lchip, p_port_isolation));
        return CTC_E_NONE;
    }


    if (0 == p_port_isolation->mode)
    {
        p_port_isolation->mode = p_port_isolation->use_isolation_id;
    }

    if (2 < p_port_isolation->mode)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "isolation mode %d, invalid parameter\n", p_port_isolation->mode);
        return CTC_E_INVALID_PARAM;
    }

    if (((1 == p_usw_port_master[lchip]->use_isolation_id) && (0 == p_port_isolation->mode))
        || ((0 == p_usw_port_master[lchip]->use_isolation_id) && ((1 == p_port_isolation->mode)|| (2 == p_port_isolation->mode))))
    {

          SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " port has another restriction feature \n");
          return CTC_E_INVALID_CONFIG;

    }
    if (1 == p_port_isolation->mode)
    {
        isolation_group = p_port_isolation->gport;
        CTC_MAX_VALUE_CHECK(isolation_group, (SYS_USW_ISOLATION_GROUP_NUM - 1));
        if (0 == p_port_isolation->gport || CTC_IS_BIT_SET(p_port_isolation->pbm[0], 0))
        {
            return CTC_E_INVALID_PARAM;
        }
        pbm = p_port_isolation->pbm[0];
        sal_memset(&ds_port_isolation, 0, sizeof(DsPortIsolation_m));
        cmd = DRV_IOR(DsPortIsolation_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, isolation_group, cmd, &ds_port_isolation));
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_UNKNOW_UCAST))
        {
            SetDsPortIsolation(A, unknownUcIsolate_f, &ds_port_isolation, &pbm);
        }
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_KNOW_UCAST))
        {
            SetDsPortIsolation(A, knownUcIsolate_f, &ds_port_isolation, &pbm);
        }
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_UNKNOW_MCAST))
        {
            SetDsPortIsolation(A, unknownMcIsolate_f, &ds_port_isolation, &pbm);
        }
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_KNOW_MCAST))
        {
            SetDsPortIsolation(A, knownMcIsolate_f, &ds_port_isolation, &pbm);
        }
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_BCAST))
        {
            SetDsPortIsolation(A, bcIsolate_f, &ds_port_isolation, &pbm);
        }
        cmd = DRV_IOW(DsPortIsolation_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, isolation_group, cmd, &ds_port_isolation));
    }
    else if (2 == p_port_isolation->mode)
    {
        CTC_ERROR_RETURN(_sys_usw_port_set_isolation_id(lchip, p_port_isolation));
    }
    else if (0 == p_port_isolation->mode)
    {
        /*verifying whether the port is configurated other mode*/
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_port_isolation->gport, lchip, lport);
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &igs_isolation_id));
        if (CTC_IS_BIT_SET(igs_isolation_id, 6))
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " port has another restriction feature \n");
            return CTC_E_INVALID_CONFIG;
        }
        CTC_ERROR_RETURN(_sys_usw_port_set_isolation_id(lchip, p_port_isolation));
    }
    else
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid parameter \n");
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_get_isolation(uint8 lchip, ctc_port_isolation_t* p_port_isolation)
{
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    if (p_port_isolation->mlag_en)
    {
        CTC_ERROR_RETURN(_sys_usw_port_get_mlag_isolation(lchip, p_port_isolation));
        return CTC_E_NONE;
    }
    if (0 == p_port_isolation->mode)
    {
        p_port_isolation->mode = p_usw_port_master[lchip]->use_isolation_id;
    }
    if (1 == p_port_isolation->mode)
    {
        uint32 cmd = 0;
        uint32 isolation_group = 0;

        isolation_group = p_port_isolation->gport;
        CTC_MAX_VALUE_CHECK(isolation_group, (SYS_USW_ISOLATION_GROUP_NUM - 1));

        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_UNKNOW_UCAST))
        {
            cmd = DRV_IOR(DsPortIsolation_t, DsPortIsolation_unknownUcIsolate_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[0]));
        }
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_KNOW_UCAST))
        {
            cmd = DRV_IOR(DsPortIsolation_t, DsPortIsolation_knownUcIsolate_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[0]));
        }
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_UNKNOW_MCAST))
        {
            cmd = DRV_IOR(DsPortIsolation_t, DsPortIsolation_unknownMcIsolate_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[0]));
        }
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_KNOW_MCAST))
        {
            cmd = DRV_IOR(DsPortIsolation_t, DsPortIsolation_knownMcIsolate_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[0]));
        }
        if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
            CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_BCAST))
        {
            cmd = DRV_IOR(DsPortIsolation_t, DsPortIsolation_bcIsolate_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[0]));
        }
        p_port_isolation->use_isolation_id = 1;
    }
    else if ((0 == p_port_isolation->mode) || (2 == p_port_isolation->mode))
    {
        uint32 cmd = 0;
        uint32 tbl_id = 0;
        uint32 igs_isolation_id = 0;
        uint16 lport = 0;
        uint32 isolation_group_mode = 0;
        uint8 isolation_group = 0;
        uint16 loop = 0;
        uint16 entry_num = 0;
        if (2 != p_port_isolation->mode)
        {
            SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_port_isolation->gport, lchip, lport);
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_srcPortIsolateId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &igs_isolation_id));

            if (CTC_IS_BIT_SET(igs_isolation_id, 6))
            {
                SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "This port has been configured another mode! \n");
                return CTC_E_NONE;
            }
        }
        if (DRV_FROM_TMM(lchip)) /* TMM: Isolation group num is 64, Max Member is 256;  AT: Isolation group num is 64, Max Member is 512 */
        {
            entry_num = MCHIP_CAP(SYS_CAP_ISOLATION_PER_GROUP_ENTRY_NUM);
        }
        else
        {
            cmd = DRV_IOR(QWritePortIsolateCtl_t, QWritePortIsolateCtl_portIsolateMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &isolation_group_mode));

            switch (isolation_group_mode)
            {
                case CTC_ISOLATION_GROUP_MODE_64:
                    entry_num = 2;
                    break;
                case CTC_ISOLATION_GROUP_MODE_32:
                    entry_num = 4;
                    break;
                case CTC_ISOLATION_GROUP_MODE_16:
                    entry_num = 8;
                    break;
                default:
                    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid parameter \n");
                    return CTC_E_INVALID_PARAM;
            }
        }
        if(2 == p_port_isolation->mode)
        {
            igs_isolation_id = p_port_isolation->gport;
            CTC_MAX_VALUE_CHECK(igs_isolation_id, (SYS_USW_ISOLATION_GROUP_NUM - 1));
        }
        for (loop = 0; loop < entry_num; loop++)
        {
            isolation_group = igs_isolation_id * entry_num + loop;
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "isolation_group: %d\n", isolation_group);
            tbl_id = DRV_FROM_AT(lchip)? DsUcQWritePortBlockMask_t: DsPortBlockMask_t;
            if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
                CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_UNKNOW_UCAST))
            {
                cmd = DRV_IOR(tbl_id, DsPortBlockMask_array_0_blockMask_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[loop]));
            }
            if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
                CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_KNOW_UCAST))
            {
                cmd = DRV_IOR(tbl_id, DsPortBlockMask_array_2_blockMask_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[loop]));
            }
            tbl_id = DRV_FROM_AT(lchip)? DsMcQWritePortBlockMask_t: DsPortBlockMask_t;
            if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
                CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_UNKNOW_MCAST))
            {
                cmd = DRV_IOR(tbl_id, DsPortBlockMask_array_1_blockMask_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[loop]));
            }
            if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
                CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_KNOW_MCAST))
            {
                cmd = DRV_IOR(tbl_id, DsPortBlockMask_array_3_blockMask_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[loop]));
            }
            if (CTC_PORT_ISOLATION_ALL == p_port_isolation->isolation_pkt_type ||
                CTC_FLAG_ISSET(p_port_isolation->isolation_pkt_type, CTC_PORT_ISOLATION_BCAST))
            {
                cmd = DRV_IOR(tbl_id, DsPortBlockMask_array_4_blockMask_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, isolation_group, cmd, &p_port_isolation->pbm[loop]));
            }
        }

        p_port_isolation->use_isolation_id = (2 == p_port_isolation->mode)?1:0;
    }

    return CTC_E_NONE;
}


STATIC int32
_sys_usw_port_set_random_log_percent(uint8 lchip, uint32 gport, ctc_direction_t dir, uint32 percent)
{
    uint16 lport = 0;
    uint16 shift = 0;
    uint32 value = 0;
    uint32 cmd = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port gport:0x%04X, direction:%d, percent:%d\n", \
                     gport, dir, percent);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    CTC_MAX_VALUE_CHECK(percent, 100);

    shift = (dir == CTC_INGRESS) ? MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT) : MCHIP_CAP(SYS_CAP_RANDOM_LOG_EGS_SHIFT);
    /* default randomLogShift = MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT) */
    if (100 > percent)
    {
        value = ((MCHIP_CAP(SYS_CAP_RANDOM_LOG_THRESHOD)/100)/(1<<shift)) * percent;
        if(value > 0x7FFF)
        {
            return CTC_E_INVALID_PARAM;
        }
    }
    else
    {
        value = 0x7FFF;
    }

    if (CTC_INGRESS == dir)
    {
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_randomThreshold_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
    }
    else if (CTC_EGRESS == dir)
    {
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_randomThreshold_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_get_random_log_percent(uint8 lchip, uint32 gport, ctc_direction_t dir, uint32* p_percent)
{
    int32 ret = CTC_E_NONE;

    uint16 lport = 0;
    uint32 value = 0;
    uint32 cmd = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port gport:0x%04X, direction:%d\n", gport, dir);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    if (CTC_INGRESS == dir)
    {
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_randomThreshold_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &value);
        if (CTC_E_NONE == ret)
        {
            /* default randomLogShift = MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT) */
            *p_percent = value  / ((MCHIP_CAP(SYS_CAP_RANDOM_LOG_THRESHOD)/100)/(1<<MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT)));
        }
    }
    else if (CTC_EGRESS == dir)
    {
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_randomThreshold_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &value);
        if (CTC_E_NONE == ret)
        {
            /* default randomLogShift = MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT) */
            *p_percent = value  / ((MCHIP_CAP(SYS_CAP_RANDOM_LOG_THRESHOD)/100)/(1<<MCHIP_CAP(SYS_CAP_RANDOM_LOG_EGS_SHIFT)));
        }
    }
    *p_percent = (*p_percent > 100) ? 100 : *p_percent;

    return ret;
}

STATIC int32
_sys_usw_port_set_random_log_rate(uint8 lchip, uint32 gport, ctc_direction_t dir, uint32 rate)
{
    int32 ret = CTC_E_NONE;

    uint16 lport = 0;
    uint32 cmd = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port gport:0x%04X, direction:%d, rate:%d\n", \
                     gport, dir, rate);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    CTC_MAX_VALUE_CHECK(rate, MCHIP_CAP(SYS_CAP_RANDOM_LOG_RATE) - 1);

    /* default randomLogShift = MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT) */
    if (CTC_INGRESS == dir)
    {
        cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_randomThreshold_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &rate);
    }
    else if (CTC_EGRESS == dir)
    {
        cmd = DRV_IOW(DsDestPort_t, DsDestPort_randomThreshold_f);
        ret = DRV_FIELD_IOCTL(lchip, lport, cmd, &rate);
    }

    return ret;
}

/**
@brief  Set port's internal properties with direction according to gport id
*/
int32
sys_usw_port_set_mirror_en(uint8 lchip , uint16 lport, uint8 type, uint32 dsfwd_offset, bool is_add)
{
    DsPhyPortExt_m phy_port_ext;
    DsPhyPort_m phy_port;
    DsSrcPort_m src_port;
    uint32 cmd = 0;
    uint32 value = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &src_port));
    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));
    cmd = DRV_IOR(DsPhyPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port));

    value = is_add? 1 : 0;
    SetDsSrcPort(V, routeDisable_f, &src_port, value);
    SetDsSrcPort(V, addDefaultVlanDisable_f, &src_port, value);
    value = is_add? 0 : 1;
    SetDsPhyPortExt(V, defaultVlanId_f, &phy_port_ext, value);
    SetDsPhyPort(V, packetTypeValid_f, &phy_port, 0);
    SetDsPhyPort(V, packetType_f, &phy_port, 0);
    if (type == 0)/*iloop*/
    {
        value = is_add? 1 : 0;
        SetDsSrcPort(V, stpDisable_f, &src_port, value);
    }
    else if(type == 1)/*mcast*/
    {
        value = is_add? 1 : 0;
        SetDsSrcPort(V, portCrossConnect_f, &src_port, value);
        SetDsSrcPort(V, bridgeEn_f, &src_port, !value);
        value = is_add? dsfwd_offset : 0;
        SetDsPhyPortExt(V, u1_g2_dsFwdPtr_f, &phy_port_ext,value);
    }

    cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &src_port));
    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port_ext));
    cmd = DRV_IOW(DsPhyPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &phy_port));

    return CTC_E_NONE;
}

int32
sys_usw_port_set_direction_property(uint8 lchip, uint32 gport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32 value)
{
    int32 ret = CTC_E_NONE;

    uint16 drv_lport = 0;
    uint32 cmd = 0;
    uint32 temp;
    uint32 egress_value = value;
    uint32 acl_lkup_type = 0;
    uint32 acl_gport_type = 0;
    uint32 dot1ae_en[8] = {0};
    QWriteDot1AeCtl_m ds_ctl;
    uint32 index = 0;
    uint8  is_support_glb_port = _sys_usw_port_is_support_glb_port(lchip);
    uint8   gchip = SYS_MAP_CTC_GPORT_TO_GCHIP(gport);
    uint32  random_en = 0;
    uint32 valid = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    ds_t   ds;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port property with direction, gport:0x%04X, property:%d, dir:%d,\
                                            value:%d\n", gport, port_prop, dir, value);

    /*Sanity check*/
    CTC_MAX_VALUE_CHECK(dir, CTC_BOTH_DIRECTION);
    SYS_GLOBAL_CHIPID_CHECK(gchip);
    if (FALSE == sys_usw_chip_is_local(lchip, gchip))
    {
        if(dir != CTC_EGRESS)
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Only support config global port's egress property\n");
            return CTC_E_INVALID_PARAM;
        }
        return _sys_usw_port_set_global_property(lchip, gport, port_prop, value);
    }
    drv_lport = CTC_MAP_GPORT_TO_LPORT(gport);
    if (drv_lport >= MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP))
    {
        return CTC_E_INVALID_PORT;
    }
    if(CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_0 == port_prop || CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_1 == port_prop ||
       CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_2 == port_prop || CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_3 == port_prop)
    {
        CTC_MAX_VALUE_CHECK(value, CTC_ACL_TCAM_LKUP_TYPE_MAX -1);
        if(CTC_ACL_TCAM_LKUP_TYPE_VLAN == value || value == CTC_ACL_TCAM_LKUP_TYPE_COPP)
        {
            return CTC_E_NOT_SUPPORT;        /* vlan not support, copp only support global configure */
        }
        acl_lkup_type = sys_usw_map_acl_tcam_lkup_type(lchip, value);
    }
    /*do write*/
    dmps_port_info.gport = gport;
    if ((CTC_INGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        switch (port_prop)
        {
        case CTC_PORT_DIR_PROP_STAG_TPID_INDEX:
            if (value > 3 && (0xff != value))
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_svlanTpidIndex_f);
            break;

        case CTC_PORT_DIR_PROP_VLAN_FILTER_EN:
            value = (value) ? SYS_PORT_VLAN_FILTER_MODE_ENABLE : SYS_PORT_VLAN_FILTER_MODE_DISABLE;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_ingressFilteringMode_f);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_EN:
            cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_randomLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &random_en));
            value = (value) ? 1 : 0;
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_randomLogEn_f);
            if ((random_en^value) && DRV_FROM_TM(lchip))      /*TM,TMM support seed id, only change random en will call the function*/
            {
                CTC_ERROR_RETURN(_sys_usw_port_set_seed_id(lchip, drv_lport, CTC_INGRESS, value));
            }
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_PERCENT:
            ret = _sys_usw_port_set_random_log_percent(lchip, gport, CTC_INGRESS, value);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_RATE:
            ret = _sys_usw_port_set_random_log_rate(lchip, gport, CTC_INGRESS, value);
            break;
/********** ACL property begin **********/
        case CTC_PORT_DIR_PROP_ACL_EN:
            if (value > (CTC_ACL_EN_0 + CTC_ACL_EN_1 + CTC_ACL_EN_2 + CTC_ACL_EN_3))
            {
                return CTC_E_INVALID_PARAM;
            }

            if (0 == value)     /* if acl dis, set acl lookup type = 0 */
            {
                cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_1_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_2_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_3_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));

                cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_1_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_2_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_3_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            }
            else
            {
                /*when acl-en,tcam lookup type is L2 and global port type is use port bitmap
                                                                           for compatible GG*/
                acl_lkup_type = SYS_ACL_TCAM_LKUP_TYPE_L2;
                acl_gport_type = 0;
                if(value & 0x1)
                {
                    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_0_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsSrcPort_t,DsSrcPort_gAcl_0_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));

                    cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsSrcPortAclCtl_t,DsSrcPortAclCtl_gAcl_0_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));
                }
                if(value & 0x2)
                {
                    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_1_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsSrcPort_t,DsSrcPort_gAcl_1_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));

                    cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_1_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsSrcPortAclCtl_t,DsSrcPortAclCtl_gAcl_1_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));
                }
                if(value & 0x4)
                {
                    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_2_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsSrcPort_t,DsSrcPort_gAcl_2_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));

                    cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_2_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsSrcPortAclCtl_t,DsSrcPortAclCtl_gAcl_2_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));
                }
                if(value & 0x8)
                {
                    cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_3_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsSrcPort_t,DsSrcPort_gAcl_3_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));

                    cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_3_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsSrcPortAclCtl_t,DsSrcPortAclCtl_gAcl_3_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));
                }
            }

            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_ACL_HASH_FIELD_SEL_ID:
            if (value > 0xF)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_aclFlowHashFieldSel_f);
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID:
        case CTC_PORT_DIR_PROP_ACL_CLASSID_0:
            SYS_USW_MAX_CLASS_ID_CHECK(value);
            if (DRV_FROM_AT(lchip)) cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclLabel_f);
            else cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_0_aclLabel_f);
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID_1:
            SYS_USW_MAX_CLASS_ID_CHECK(value);
            if (DRV_FROM_AT(lchip)) cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_1_aclLabel_f);
            else cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_1_aclLabel_f);
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID_2:
            SYS_USW_MAX_CLASS_ID_CHECK(value);
            if (DRV_FROM_AT(lchip)) cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_2_aclLabel_f);
            else cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_2_aclLabel_f);
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID_3:
            SYS_USW_MAX_CLASS_ID_CHECK(value);
            if (DRV_FROM_AT(lchip)) cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_3_aclLabel_f);
            else cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_3_aclLabel_f);
            break;

        case CTC_PORT_DIR_PROP_ACL_USE_CLASSID:
            acl_gport_type = value? DRV_ENUM(DRV_FLOWPORTTYPE_GPORT): DRV_ENUM(DRV_FLOWPORTTYPE_BITMAP);
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, drv_lport, cmd, ds));
                SetDsSrcPortAclCtl(V, gAcl_0_aclUseGlobalPortType_f, ds, acl_gport_type);
                SetDsSrcPortAclCtl(V, gAcl_1_aclUseGlobalPortType_f, ds, acl_gport_type);
                SetDsSrcPortAclCtl(V, gAcl_2_aclUseGlobalPortType_f, ds, acl_gport_type);
                SetDsSrcPortAclCtl(V, gAcl_3_aclUseGlobalPortType_f, ds, acl_gport_type);
                cmd = DRV_IOW(DsSrcPortAclCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, drv_lport, cmd, ds));
            }
            else
            {
                cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, drv_lport, cmd, ds));
                SetDsSrcPort(V, gAcl_0_aclUseGlobalPortType_f, ds, acl_gport_type);
                SetDsSrcPort(V, gAcl_1_aclUseGlobalPortType_f, ds, acl_gport_type);
                SetDsSrcPort(V, gAcl_2_aclUseGlobalPortType_f, ds, acl_gport_type);
                SetDsSrcPort(V, gAcl_3_aclUseGlobalPortType_f, ds, acl_gport_type);
                cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, drv_lport, cmd, ds));
            }
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_ACL_HASH_LKUP_TYPE:
            if(SYS_FTM_SPEC(lchip, CTC_FTM_SPEC_ACL_FLOW) == 0)
            {
                return CTC_E_NO_RESOURCE;
            }
            if (value > CTC_ACL_HASH_LKUP_TYPE_MAX -1)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_aclFlowHashType_f);
            break;
        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_0:
            cmd = DRV_FROM_AT(lchip) ? DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclLookupType_f)
                                     : DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_0_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_1:
            cmd = DRV_FROM_AT(lchip) ? DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_1_aclLookupType_f)
                                     : DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_1_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_2:
            cmd = DRV_FROM_AT(lchip) ? DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_2_aclLookupType_f)
                                     : DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_2_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_3:
            cmd = DRV_FROM_AT(lchip) ? DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_3_aclLookupType_f)
                                     : DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_3_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_ACL_USE_MAPPED_VLAN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_0_aclUsePIVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_1_aclUsePIVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_2_aclUsePIVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_gAcl_3_aclUsePIVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));

            cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclUsePIVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_1_aclUsePIVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_2_aclUsePIVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_3_aclUsePIVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_ACL_PORT_BITMAP_ID:
            if (value > MCHIP_CAP(SYS_CAP_ACL_PORT_BITMAP_NUM))
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_FROM_AT(lchip)
                    ? DRV_IOW(DsSrcPortAclCtl_t, DsSrcPortAclCtl_aclPortNum_f)
                    : DRV_IOW(DsSrcPort_t, DsSrcPort_aclPortNum_f);
            break;
        case CTC_PORT_DIR_PROP_SERVICE_ACL_EN:
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Feature not supported \n");
            return CTC_E_NOT_SUPPORT;


/********** ACL property end **********/
        case CTC_PORT_DIR_PROP_QOS_DOMAIN:
            if (value > MCHIP_CAP(SYS_CAP_QOS_CLASS_COS_DOMAIN_MAX))
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_cosPhbPtr_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_dscpPhbPtr_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            break;

        case CTC_PORT_DIR_PROP_QOS_COS_DOMAIN:
            if (value > MCHIP_CAP(SYS_CAP_QOS_CLASS_COS_DOMAIN_MAX))
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_cosPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_QOS_DSCP_DOMAIN:
            if (value > MCHIP_CAP(SYS_CAP_QOS_CLASS_DSCP_DOMAIN_MAX))
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_dscpPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_DOT1AE_EN:
            {
                sys_com_dot1ae_bind_sc_t bind_sc;
                sal_memset(&bind_sc, 0, sizeof(bind_sc));
                value = (value) ? 1 : 0;
                bind_sc.type = 0;
                bind_sc.gport = gport;
                bind_sc.dir = 1; /* CTC_DOT1AE_SC_DIR_RX */
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                if (DRV_FROM_TMM(lchip))
                {
                    bind_sc.dot1AE_RX_En = value;
                    if (MCHIP_1AE(lchip)->en_sec_chan)
                    {
                        CTC_ERROR_RETURN(MCHIP_1AE(lchip)->en_sec_chan(lchip, &bind_sc));
                        CTC_ERROR_RETURN(MCHIP_1AE(lchip)->get_en_sec_chan(lchip, &bind_sc));
                    }
                    else
                    {
                        return CTC_E_NOT_SUPPORT;
                    }
                }
                else
                {
                    if (value)/*enable*/
                    {
                        if (SYS_CB_PTR(SYS_CB_DOT1AE_GET_BIND_SEC_CHAN))
                        {
                            bind_sc.p_chan_id = mem_malloc(MEM_PORT_MODULE,  MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM)*sizeof(uint32));
                            if (NULL == bind_sc.p_chan_id)
                            {
                                return CTC_E_NO_MEMORY;
                            }
                            sal_memset(bind_sc.p_chan_id, 0, MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM)*sizeof(uint32));
                            ret = SYS_CB(SYS_CB_DOT1AE_GET_BIND_SEC_CHAN, lchip, &bind_sc);
                            if (ret < 0)
                            {
                                mem_free(bind_sc.p_chan_id);
                                return ret;
                            }
                            if (0 == bind_sc.p_chan_id[0])
                            {
                                mem_free(bind_sc.p_chan_id);
                                return CTC_E_NOT_READY;
                            }
                            mem_free(bind_sc.p_chan_id);
                        }
                        else
                        {
                            return CTC_E_NOT_SUPPORT;
                        }
                    }
                    cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_dot1AeSaIndex_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &temp));
                    bind_sc.sc_index = temp >> 2;
                }

                value = value ? 1 : 0;
                cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_dot1AeP2pMode0En_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_dot1AeP2pMode1En_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_dot1AeP2pMode2En_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                value = value ? 0xFFFF : 0;
                cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_macsecPduBitmap_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));

                value = value ? 1 : 0;
                cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_dot1AeEn_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_CHAN_ID:
            {
                sys_com_dot1ae_bind_sc_t bind_sc;
                sal_memset(&bind_sc, 0, sizeof(bind_sc));
                bind_sc.type = 0;
                bind_sc.gport = gport;
                bind_sc.dir = 1; /* CTC_DOT1AE_SC_DIR_RX */
                bind_sc.chan_id = value;
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                if (0 != value)
                {/* bind sec-chan */
                    CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_BIND_SEC_CHAN, lchip, &bind_sc));
                }
                else
                {/* chan_id 0 is used to unbinded */
                    CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_SUPPORT, SYS_CB_DOT1AE_UNBIND_SEC_CHAN, lchip, &bind_sc));
                }
                value = bind_sc.chan_id ? bind_sc.sc_index << 2 : 0;
                cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_dot1AeSaIndex_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_HASH_TYPE:
        {
            sys_com_dot1ae_hash_type_t hash_type;
            hash_type.dir = 0;
            hash_type.gport = gport;
            hash_type.type = value;
            hash_type.is_set = 1;
            SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
            CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_SET_HASH_TYPE, lchip, &hash_type));
        }
            break;
        case CTC_PORT_DIR_PROP_SD_ACTION :
            ret = _sys_usw_port_set_sd_action(lchip, CTC_INGRESS, drv_lport, value);
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_MAX_FRAME_SIZE:
            ret = sys_usw_port_set_property(lchip, gport, CTC_PORT_PROP_MAX_FRAME_SIZE, value);
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_MAC_EN:
            value = (value) ? TRUE : FALSE;
            ret = sys_usw_dmps_set_direction_property(lchip, gport, port_prop, CTC_INGRESS, value);
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_VLAN_DOMAIN:
            CTC_MAX_VALUE_CHECK(value, CTC_PORT_VLAN_DOMAIN_MAX - 1);
            cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_outerVlanIsCVlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_flowL2KeyUseCvlan_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_FROM_TMM(lchip)? DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_sclFlowL2KeyUseCvlan_f):
                    DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_sclFlowL2KeyUseCvlan_f);
            break;
        case CTC_PORT_DIR_PROP_PTP_RESIDENCE_TIME_MODE:
            value = (value) ? TRUE : FALSE;
            cmd = DRV_IOW(DsSrcChannel_t, DsSrcChannel_srcIsPtpNewNode_f);
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &index));
            if (!SYS_IS_NETWORK_CHANNEL(index))
            {
                return CTC_E_INVALID_PARAM;
            }
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_FLOW_LKUP_BY_OUTER_HEAD:
            value = (value) ? TRUE : FALSE;
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_aclQosUseOuterInfo_f);
            break;
        case CTC_PORT_DIR_PROP_AWARE_TUNNEL_INFO_EN:
            value = (value) ? TRUE : FALSE;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_aclKeyMergeInnerAndOuterHdr_f);
            break;
        case CTC_PORT_DIR_PROP_CID:
            {
                ds_t ds_port;
                uint16 cid = 0;
                uint8 station_move_mode = 0;
                sys_usw_global_get_station_move_mode(lchip, &station_move_mode);
                if ( ((value) == CTC_ACL_UNKNOWN_CID && !DRV_FROM_TMM(lchip)) || 
                    ((value) > ( MCHIP_CAP(SYS_CAP_ACL_MAX_CID_VALUE) >> (station_move_mode? 4 : 0))))
                {
                    return CTC_E_BADID;
                }
                cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
                ret = DRV_IOCTL(lchip, drv_lport, cmd, &ds_port);
                cid = GetDsSrcPort(V, categoryId_f, ds_port);
                cid = station_move_mode? ((cid&0xF000) | value) : value;
                SetDsSrcPort(V, categoryId_f, ds_port, cid);
                cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
                ret = DRV_IOCTL(lchip, drv_lport, cmd, &ds_port);   

                value = ((cid&0xF000) | value)? 1 : 0;
                cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_categoryIdValid_f);
            }
            break;

        default:
            return CTC_E_INVALID_PARAM;
        }

        if (cmd)
        {
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
        }
    }

    value = egress_value;

    if ((CTC_EGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        index = drv_lport;
        switch (port_prop)
        {
        case CTC_PORT_DIR_PROP_STAG_TPID_INDEX:
            if (value > 3 && (0xff != value))
            {
                return CTC_E_INVALID_PARAM;
            }
            valid = (0xff == value) ? 0 : 1;
            value = (0xff == value) ? 0 : value;
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_svlanTpidValid_f) : DRV_IOW(DsDestPort_t, DsDestPort_svlanTpidValid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &valid));
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_svlanTpidIndex_f):DRV_IOW(DsDestPort_t, DsDestPort_svlanTpidIndex_f);
            break;

        case CTC_PORT_DIR_PROP_VLAN_FILTER_EN:
            value = (value) ? SYS_PORT_VLAN_FILTER_MODE_ENABLE : SYS_PORT_VLAN_FILTER_MODE_DISABLE;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_egressFilteringMode_f);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_EN:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_randomLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &random_en));
            value = (value) ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_randomLogEn_f);
            if ((random_en^value) && DRV_FROM_TM(lchip))      /*TM,TMM support seed id, only change random en will call the function*/
            {
                CTC_ERROR_RETURN(_sys_usw_port_set_seed_id(lchip, drv_lport, CTC_EGRESS, value));
            }
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_PERCENT:
            ret = _sys_usw_port_set_random_log_percent(lchip, gport, CTC_EGRESS, value);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_RATE:
            ret = _sys_usw_port_set_random_log_rate(lchip, gport, CTC_EGRESS, value);
            break;
/********** ACL property begin **********/
        case CTC_PORT_DIR_PROP_ACL_EN:
            if(value>CTC_ACL_EN_0)
            {
                return CTC_E_INVALID_PARAM;
            }
            if (0 == value)     /* if acl dis, set l2 label = 0 */
            {
                cmd = DRV_IOW(DsDestPort_t, DsDestPort_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));

                cmd = DRV_IOW(DsDestPortAclCtl_t, DsDestPortAclCtl_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            }
            else
            {
                acl_lkup_type = 1;
                acl_gport_type = 0;
                if(value & 0x1)
                {
                    cmd = DRV_IOW(DsDestPort_t, DsDestPort_gAcl_0_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsDestPort_t,DsDestPort_gAcl_0_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));

                    cmd = DRV_IOW(DsDestPortAclCtl_t, DsDestPortAclCtl_gAcl_0_aclLookupType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
                    cmd = DRV_IOW(DsDestPortAclCtl_t,DsDestPortAclCtl_gAcl_0_aclUseGlobalPortType_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip,drv_lport,cmd,&acl_gport_type));
                }
            }
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID:
        case CTC_PORT_DIR_PROP_ACL_CLASSID_0:
            SYS_USW_MAX_CLASS_ID_CHECK(value);
            if(DRV_FROM_AT(lchip)) cmd = DRV_IOW(DsDestPortAclCtl_t, DsDestPortAclCtl_gAcl_0_aclLabel_f);
            else cmd = DRV_IOW(DsDestPort_t, DsDestPort_gAcl_0_aclLabel_f);
            break;
        case CTC_PORT_DIR_PROP_ACL_USE_CLASSID:
            acl_gport_type = value? DRV_ENUM(DRV_FLOWPORTTYPE_GPORT): DRV_ENUM(DRV_FLOWPORTTYPE_BITMAP);
            if (DRV_FROM_AT(lchip)) cmd = DRV_IOW(DsDestPortAclCtl_t, DsDestPortAclCtl_gAcl_0_aclUseGlobalPortType_f);
            else cmd = DRV_IOW(DsDestPort_t, DsDestPort_gAcl_0_aclUseGlobalPortType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_gport_type));
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_SERVICE_ACL_EN:
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Feature not supported \n");
            return CTC_E_NOT_SUPPORT;


        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_0:
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_gAcl_0_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));

            cmd = DRV_IOW(DsDestPortAclCtl_t, DsDestPortAclCtl_gAcl_0_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &acl_lkup_type));
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_ACL_PORT_BITMAP_ID:
            if(value>MCHIP_CAP(SYS_CAP_PORT_BITMAP_NUM)-1)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_FROM_AT(lchip)
                    ? DRV_IOW(DsDestPortAclCtl_t, DsDestPortAclCtl_aclPortNum_f)
                    : DRV_IOW(DsDestPort_t, DsDestPort_aclPortNum_f);
            break;

/********** ACL property end **********/
        case CTC_PORT_DIR_PROP_QOS_DOMAIN:
            if(value>MCHIP_CAP(SYS_CAP_QOS_CLASS_COS_DOMAIN_MAX))
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_cosPhbPtr_f):DRV_IOW(DsDestPort_t, DsDestPort_cosPhbPtr_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dscpPhbPtr_f):DRV_IOW(DsDestPort_t, DsDestPort_dscpPhbPtr_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            break;

        case CTC_PORT_DIR_PROP_QOS_COS_DOMAIN:
            if(value>MCHIP_CAP(SYS_CAP_QOS_CLASS_COS_DOMAIN_MAX))
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_cosPhbPtr_f):DRV_IOW(DsDestPort_t, DsDestPort_cosPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_QOS_DSCP_DOMAIN:
            if(value>MCHIP_CAP(SYS_CAP_QOS_CLASS_DSCP_DOMAIN_MAX))
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_dscpPhbPtr_f):DRV_IOW(DsDestPort_t, DsDestPort_dscpPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_DOT1AE_EN:
            {
                sys_com_dot1ae_bind_sc_t bind_sc;
                value = value ? 1 : 0;
                sal_memset(&bind_sc, 0, sizeof(bind_sc));
                bind_sc.type = 0;
                bind_sc.gport = gport;
                bind_sc.dir = 0; /* CTC_DOT1AE_SC_DIR_TX */
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                if (DRV_FROM_TMM(lchip))
                {
                    bind_sc.dot1AE_TX_En = value;
                    if (MCHIP_1AE(lchip)->en_sec_chan)
                    {
                        CTC_ERROR_RETURN(MCHIP_1AE(lchip)->en_sec_chan(lchip, &bind_sc));
                        CTC_ERROR_RETURN(MCHIP_1AE(lchip)->get_en_sec_chan(lchip, &bind_sc));
                    }
                    else
                    {
                        return CTC_E_NOT_SUPPORT;
                    }
                }
                else
                {
                    if (value)/*enable*/
                    {
                        if (SYS_CB_PTR(SYS_CB_DOT1AE_GET_BIND_SEC_CHAN))
                        {
                            bind_sc.p_chan_id = mem_malloc(MEM_PORT_MODULE,  MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM)*sizeof(uint32));
                            if (NULL == bind_sc.p_chan_id)
                            {
                                return CTC_E_NO_MEMORY;
                            }
                            sal_memset(bind_sc.p_chan_id, 0, MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM)*sizeof(uint32));
                            ret = SYS_CB(SYS_CB_DOT1AE_GET_BIND_SEC_CHAN, lchip, &bind_sc);
                            if (ret < 0)
                            {
                                mem_free(bind_sc.p_chan_id);
                                return ret;
                            }
                            if (0 == bind_sc.p_chan_id[0])
                            {
                                mem_free(bind_sc.p_chan_id);
                                return CTC_E_NOT_READY;
                            }
                            mem_free(bind_sc.p_chan_id);
                        }
                        else
                        {
                            return CTC_E_NOT_SUPPORT;
                        }
                    }
                    cmd = DRV_IOR(DsDestPort_t, DsDestPort_dot1AeSaIndex_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &temp));
                    bind_sc.sc_index = temp >> 2;
                }
            }
            sal_memset(&ds_ctl, 0, sizeof(QWriteDot1AeCtl_m));
            cmd = DRV_IOR(QWriteDot1AeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds_ctl));
            GetQWriteDot1AeCtl(A, dot1AeEn_f, &ds_ctl, dot1ae_en);
            if (value)   /* enable */
            {
                CTC_BIT_SET(dot1ae_en[drv_lport / 32], drv_lport % 32);
            }
            else
            {
                CTC_BIT_UNSET(dot1ae_en[drv_lport / 32], drv_lport % 32);
            }
            SetQWriteDot1AeCtl(A, dot1AeEn_f, &ds_ctl, dot1ae_en);
            cmd = DRV_IOW(QWriteDot1AeCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds_ctl));

            value = value ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_dot1AeEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_CHAN_ID:
            {
                sys_com_dot1ae_bind_sc_t bind_sc;
                sal_memset(&bind_sc,0,sizeof(bind_sc));
                bind_sc.type = 0;
                bind_sc.gport = gport;
                bind_sc.dir = 0; /* CTC_DOT1AE_SC_DIR_TX */
                bind_sc.chan_id = value;
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                if (0 != bind_sc.chan_id)
                {/* bind sec-chan */
                    CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_BIND_SEC_CHAN, lchip , &bind_sc));
                }
                else
                {/* chan_id = 0, unbind sec-chan */
                    CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_SUPPORT, SYS_CB_DOT1AE_UNBIND_SEC_CHAN, lchip , &bind_sc));
                }
                value = bind_sc.chan_id ? bind_sc.include_sci : 0;
                cmd = DRV_IOW(DsDestPort_t, DsDestPort_dot1AeSciEn_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
                value = bind_sc.chan_id ? (bind_sc.sc_index << 2) : 0;
                cmd = DRV_IOW(DsDestPort_t, DsDestPort_dot1AeSaIndex_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_HASH_TYPE:
        {
            sys_com_dot1ae_hash_type_t hash_type;
            hash_type.dir = 1;
            hash_type.gport = gport;
            hash_type.type = value;
            hash_type.is_set = 1;
            SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
            CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_SET_HASH_TYPE, lchip, &hash_type));
        }
            break;

        case CTC_PORT_DIR_PROP_SD_ACTION :
            ret = _sys_usw_port_set_sd_action(lchip, CTC_EGRESS, index, value);
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_MAX_FRAME_SIZE:
            {
                uint8 frame_idx = 0;
                uint32 tmp_val = 0;
                uint32 max_frame = 0;
                uint32 mac_id = 0;

                if ((value < MCHIP_CAP(SYS_CAP_PORT_MAX_FRAMESIZE_MIN_VALUE)) || (value > MCHIP_CAP(SYS_CAP_PORT_MAX_FRAMESIZE_MAX_VALUE)))
                {
                    return CTC_E_INVALID_PARAM;
                }
                if (!(SYS_DMPS_NETWORK_PORT == sys_usw_is_network_port(lchip, gport)))
                {
                    return CTC_E_INVALID_PORT;
                }
                if (DRV_FROM_AT(lchip))
                {
                    uint32 pp_id = 0;
                    uint32 dp_id = 0;
                    uint32 sub_chan = 0;
                    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SUB_CHAN_ID, &sub_chan));
                    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, &dp_id));
                    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
                    cmd = DRV_IOW(NetTxMaxMinLenCfg_t, NetTxMaxMinLenCfg_cfgMaxPktLen_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(SYS_PP_BASE(lchip) + pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &value));
                    cmd = 0;
                }
                else if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
                {
                    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, &mac_id));
                    cmd = DRV_IOW(NetTxMaxMinLenCfg_t, NetTxMaxMinLenCfg_cfgMaxPktLen_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, mac_id, cmd, &value));
                    cmd = 0;
                }
                else
                {
                    cmd = DRV_IOR(NetTxMaxMinLenPortMap_t, NetTxMaxMinLenPortMap_maxLenPortSel_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &tmp_val));
                    cmd = DRV_IOR(NetTxMaxLenCfg_t, NetTxMaxLenCfg_maxCheckLen_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, tmp_val, cmd, &max_frame));
                    CTC_ERROR_RETURN(_sys_usw_port_add_tx_max_frame_size(lchip, value, max_frame, &frame_idx));
                    tmp_val = frame_idx;
                    cmd = DRV_IOW(NetTxMaxMinLenPortMap_t, NetTxMaxMinLenPortMap_maxLenPortSel_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &tmp_val));
                    cmd = 0;
                }
            }
            break;
        case CTC_PORT_DIR_PROP_MAC_EN:
            value = (value) ? TRUE : FALSE;
            ret = sys_usw_dmps_set_direction_property(lchip, gport, port_prop, CTC_EGRESS, value);
            break;
        case CTC_PORT_DIR_PROP_VLAN_DOMAIN:
            CTC_MAX_VALUE_CHECK(value, CTC_PORT_VLAN_DOMAIN_MAX - 1);
            cmd = is_support_glb_port ? DRV_IOW(DsGlbDestPort_t, DsGlbDestPort_cvlanSpace_f):DRV_IOW(DsDestPort_t, DsDestPort_cvlanSpace_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, drv_lport, cmd, &value));
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_flowL2KeyUseCvlan_f);
            break;
        case CTC_PORT_DIR_PROP_PTP_RESIDENCE_TIME_MODE:
            value = (value) ? TRUE : FALSE;
            cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_dstIsPtpNewNode_f);
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &index));
            break;
        case CTC_PORT_DIR_PROP_FLOW_LKUP_BY_OUTER_HEAD:
            value = (value) ? FALSE : TRUE;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_aclQosUseInnerInfo_f);
            index = drv_lport;
            break;
        case CTC_PORT_DIR_PROP_AWARE_TUNNEL_INFO_EN:
            value = (value) ? TRUE : FALSE;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_aclKeyMergeInnerAndOuterHdr_f);
            index = drv_lport;
            break;
        case CTC_PORT_DIR_PROP_CID:
            if ((value) > MCHIP_CAP(SYS_CAP_ACL_MAX_CID_VALUE) )
            {
                return CTC_E_BADID;
             }
            cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);/*AT*/
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, drv_lport, cmd, ds));
            SetDsDestPort(V, categoryId_f, ds, value);
            SetDsDestPort(V, categoryIdValid_f, ds, (value)?1:0);
            cmd = DRV_IOW(DsDestPort_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, drv_lport, cmd, ds));
            cmd = 0;
            break;
        default:
            return CTC_E_INVALID_PARAM;
        }

        if (cmd)
        {
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value));
        }
    }

    CTC_ERROR_RETURN(ret);
    return CTC_E_NONE;
}

int32
sys_usw_port_get_direction_property(uint8 lchip, uint32 gport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32* p_value)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    int32  ret = CTC_E_NONE;
    uint32 acl_en = 0;
    uint32 acl_lkup_type = 0;
    uint32 acl_gport_type;
    uint32 index = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    sys_com_dot1ae_bind_sc_t bind_sc;
    ctc_dot1ae_an_stats_t* p_secy_stats=NULL;
    uint8  is_support_glb_port = _sys_usw_port_is_support_glb_port(lchip);
    uint8   gchip = SYS_MAP_CTC_GPORT_TO_GCHIP(gport);

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port property with direction, gport:0x%04X, property:%d, dir:%d\n" \
                     , gport, port_prop, dir);

    sal_memset(&bind_sc,0,sizeof(bind_sc));
    p_secy_stats = (ctc_dot1ae_an_stats_t*)p_value;
    /*Sanity check*/
    CTC_PTR_VALID_CHECK(p_value);
    CTC_MAX_VALUE_CHECK(dir, CTC_BOTH_DIRECTION - 1);
    SYS_GLOBAL_CHIPID_CHECK(gchip);
    if (FALSE == sys_usw_chip_is_local(lchip, gchip))
    {
        if(dir != CTC_EGRESS)
        {
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Only support config global port's egress property\n");
            return CTC_E_INVALID_PARAM;
        }
        return _sys_usw_port_get_global_property(lchip, gport, port_prop, p_value);
    }
    lport = CTC_MAP_GPORT_TO_LPORT(gport);
    if (lport >= MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP))
    {
        return CTC_E_INVALID_PORT;
    }
    /* zero value */
    *p_value = 0;
    index = lport;
    dmps_port_info.gport = gport;

    /*do read,only get value by CTC_INGRESS or CTC_EGRESS,no CTC_BOTH_DIRECTION*/
    if (CTC_INGRESS == dir)
    {
        switch (port_prop)
        {
        case CTC_PORT_DIR_PROP_STAG_TPID_INDEX:
            cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_svlanTpidIndex_f);
            break;

        case CTC_PORT_DIR_PROP_VLAN_FILTER_EN:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_ingressFilteringMode_f);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_EN:
            cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_randomLogEn_f);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_PERCENT:
            ret = _sys_usw_port_get_random_log_percent(lchip, gport, dir, p_value);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_RATE:
            cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_randomThreshold_f);
            /* default randomLogShift = MCHIP_CAP(SYS_CAP_RANDOM_LOG_SHIFT)*/
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, p_value));
            cmd = 0;
            break;
/********** ACL property begin **********/
        case CTC_PORT_DIR_PROP_ACL_EN:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
                if (acl_en)
                {
                    CTC_SET_FLAG(*p_value, CTC_ACL_EN_0);
                }
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_1_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
                if (acl_en)
                {
                    CTC_SET_FLAG(*p_value, CTC_ACL_EN_1);
                }
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_2_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
                if (acl_en)
                {
                    CTC_SET_FLAG(*p_value, CTC_ACL_EN_2);
                }
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_3_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
                if (acl_en)
                {
                    CTC_SET_FLAG(*p_value, CTC_ACL_EN_3);
                }
            }
            else
            {
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
                if (acl_en)
                {
                    CTC_SET_FLAG(*p_value, CTC_ACL_EN_0);
                }
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_1_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
                if (acl_en)
                {
                    CTC_SET_FLAG(*p_value, CTC_ACL_EN_1);
                }
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_2_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
                if (acl_en)
                {
                    CTC_SET_FLAG(*p_value, CTC_ACL_EN_2);
                }
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_3_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
                if (acl_en)
                {
                    CTC_SET_FLAG(*p_value, CTC_ACL_EN_3);
                }
            }

            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID:
        case CTC_PORT_DIR_PROP_ACL_CLASSID_0:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclLabel_f);
            }
            else
            {
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_0_aclLabel_f);
            }
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID_1:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_1_aclLabel_f);
            }
            else
            {
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_1_aclLabel_f);
            }
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID_2:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_2_aclLabel_f);
            }
            else
            {
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_2_aclLabel_f);
            }
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID_3:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_3_aclLabel_f);
            }
            else
            {
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_3_aclLabel_f);
            }
            break;

        case CTC_PORT_DIR_PROP_ACL_USE_CLASSID:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_0_aclUseGlobalPortType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_gport_type));
            if(acl_gport_type == DRV_ENUM(DRV_FLOWPORTTYPE_GPORT))
            {
                *p_value = 1;
            }
            else
            {
                *p_value = 0;
            }
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_ACL_HASH_FIELD_SEL_ID:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_aclFlowHashFieldSel_f);
            break;

        case CTC_PORT_DIR_PROP_SERVICE_ACL_EN:
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Feature not supported \n");
            return CTC_E_NOT_SUPPORT;

            break;

        case CTC_PORT_DIR_PROP_ACL_HASH_LKUP_TYPE:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_aclFlowHashType_f);
            break;

        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_0:
            cmd = DRV_FROM_AT(lchip) ? DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclLookupType_f)
                                     : DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_0_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_lkup_type));
            *p_value = sys_usw_unmap_acl_tcam_lkup_type(lchip, acl_lkup_type);
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_1:
            cmd = DRV_FROM_AT(lchip) ? DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_1_aclLookupType_f)
                                     : DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_1_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_lkup_type));

            *p_value = sys_usw_unmap_acl_tcam_lkup_type(lchip, acl_lkup_type);
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_2:
            cmd = DRV_FROM_AT(lchip) ? DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_2_aclLookupType_f)
                                     : DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_2_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_lkup_type));
            *p_value = sys_usw_unmap_acl_tcam_lkup_type(lchip, acl_lkup_type);
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_3:
            cmd = DRV_FROM_AT(lchip) ? DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_3_aclLookupType_f)
                                     : DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_3_aclLookupType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_lkup_type));
            *p_value = sys_usw_unmap_acl_tcam_lkup_type(lchip, acl_lkup_type);
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_USE_MAPPED_VLAN:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_gAcl_0_aclUsePIVlan_f);
            }
            else
            {
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_gAcl_0_aclUsePIVlan_f);
            }

            break;
        case CTC_PORT_DIR_PROP_ACL_PORT_BITMAP_ID:
            cmd = DRV_FROM_AT(lchip)
                    ? DRV_IOR(DsSrcPortAclCtl_t, DsSrcPortAclCtl_aclPortNum_f)
                    : DRV_IOR(DsSrcPort_t, DsSrcPort_aclPortNum_f);
            break;
/********** ACL property end **********/
        case CTC_PORT_DIR_PROP_QOS_DOMAIN:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_cosPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_QOS_COS_DOMAIN:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_cosPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_QOS_DSCP_DOMAIN:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_dscpPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_DOT1AE_EN:
            SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
            if (DRV_FROM_TMM(lchip))
            {
                bind_sc.type = 0;
                bind_sc.gport = gport;
                bind_sc.dir = 1; /* CTC_DOT1AE_SC_DIR_RX */
                    if (MCHIP_1AE(lchip)->get_en_sec_chan)
                    {
                        CTC_ERROR_RETURN(MCHIP_1AE(lchip)->get_en_sec_chan(lchip, &bind_sc));
                    }
                    else
                    {
                        return CTC_E_NOT_SUPPORT;
                    }
                    *p_value = bind_sc.enable;
                    cmd = 0;
            }
            else
            {
                cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_dot1AeEn_f);
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_CHAN_ID:
            {

                bind_sc.type = 0;
                bind_sc.gport = gport;
                bind_sc.dir = 1; /* CTC_DOT1AE_SC_DIR_RX */
                bind_sc.p_chan_id = mem_malloc(MEM_PORT_MODULE,  MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM)*sizeof(uint32));
                if (NULL == bind_sc.p_chan_id)
                {
                    return CTC_E_NO_MEMORY;
                }
                sal_memset(bind_sc.p_chan_id, 0,MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM)*sizeof(uint32));
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                ret = SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_GET_BIND_SEC_CHAN, lchip, &bind_sc);
                if (ret < 0)
                {
                    mem_free(bind_sc.p_chan_id);
                    return ret;
                }
                if (bind_sc.SecYP2MP)
                {
                    sal_memcpy(p_value, bind_sc.p_chan_id, sizeof(uint32)*MCHIP_CAP(SYS_CAP_DOT1AE_RX_CHAN_NUM));
                }
                else
                {
                    *p_value = bind_sc.p_chan_id[0];
                }
                mem_free(bind_sc.p_chan_id);
                cmd = 0;
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_HASH_TYPE:
            {
                sys_com_dot1ae_hash_type_t hash_type;
                sal_memset(&hash_type, 0, sizeof(sys_com_dot1ae_hash_type_t));
                hash_type.is_set =0;
                hash_type.dir =0;
                hash_type.gport =gport;
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_SET_HASH_TYPE, lchip, &hash_type));
                *p_value = hash_type.type;
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_STATS:
            {
                if (!DRV_FROM_TMM(lchip))
                {
                    return CTC_E_NOT_SUPPORT;
                }
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_GET_SECY_STATS, lchip, gport, !dir, p_secy_stats));
            }
            break;
        case CTC_PORT_DIR_PROP_SD_ACTION :
            ret = _sys_usw_port_get_sd_action(lchip, CTC_INGRESS, index, p_value);
            break;

        case CTC_PORT_DIR_PROP_MAX_FRAME_SIZE:
            ret = sys_usw_port_get_property(lchip, gport, CTC_PORT_PROP_MAX_FRAME_SIZE, p_value);
            break;
        case CTC_PORT_DIR_PROP_MAC_EN:
            ret = sys_usw_dmps_get_direction_property(lchip, gport, port_prop, CTC_INGRESS, p_value);
            break;
        case CTC_PORT_DIR_PROP_VLAN_DOMAIN:
            cmd = DRV_IOR(DsPhyPort_t, DsPhyPort_outerVlanIsCVlan_f);
            break;

        case CTC_PORT_DIR_PROP_PTP_RESIDENCE_TIME_MODE:
            cmd = DRV_IOR(DsSrcChannel_t, DsSrcChannel_srcIsPtpNewNode_f);
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &index));
            if (!SYS_IS_NETWORK_CHANNEL(index))
            {
                return CTC_E_INVALID_PARAM;
            }
            break;
        case CTC_PORT_DIR_PROP_FLOW_LKUP_BY_OUTER_HEAD:
            cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_aclQosUseOuterInfo_f);
            index = lport;
            break;
        case CTC_PORT_DIR_PROP_AWARE_TUNNEL_INFO_EN:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_aclKeyMergeInnerAndOuterHdr_f);
            index = lport;
            break;
        case CTC_PORT_DIR_PROP_CID:
            {
                uint8 station_move_mode = 0;
                sys_usw_global_get_station_move_mode(lchip, &station_move_mode);
                cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_categoryId_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, p_value));
                if (station_move_mode)
                {
                    *p_value &= 0xFFF;
                }
                cmd = 0;
            }
            break;
        default:
            return CTC_E_INVALID_PARAM;

        }
    }
    else
    {
        switch (port_prop)
        {
        case CTC_PORT_DIR_PROP_STAG_TPID_INDEX:
            cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_svlanTpidIndex_f):DRV_IOR(DsDestPort_t, DsDestPort_svlanTpidIndex_f);
            break;

        case CTC_PORT_DIR_PROP_VLAN_FILTER_EN:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_egressFilteringMode_f);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_EN:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_randomLogEn_f);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_PERCENT:
            ret = _sys_usw_port_get_random_log_percent(lchip, gport, dir, p_value);
            break;

        case CTC_PORT_DIR_PROP_RANDOM_LOG_RATE:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_randomThreshold_f);
            break;
/********** ACL property begin **********/
        case CTC_PORT_DIR_PROP_ACL_EN:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsDestPortAclCtl_t, DsDestPortAclCtl_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
            }
            else
            {
                cmd = DRV_IOR(DsDestPort_t, DsDestPort_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_en));
            }
            if (acl_en)
            {
                CTC_SET_FLAG(*p_value, CTC_ACL_EN_0);
            }

            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_ACL_CLASSID:
        case CTC_PORT_DIR_PROP_ACL_CLASSID_0:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsDestPortAclCtl_t, DsDestPortAclCtl_gAcl_0_aclLabel_f);
            }
            else
            {
                cmd = DRV_IOR(DsDestPort_t, DsDestPort_gAcl_0_aclLabel_f);
            }
            break;

        case CTC_PORT_DIR_PROP_ACL_USE_CLASSID:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_gAcl_0_aclUseGlobalPortType_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_gport_type));
            if(acl_gport_type == DRV_ENUM(DRV_FLOWPORTTYPE_GPORT))
            {
                *p_value = 1;
            }
            else
            {
                *p_value = 0;
            }
            cmd = 0;
            break;

        case CTC_PORT_DIR_PROP_SERVICE_ACL_EN:
            SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Feature not supported \n");
            return CTC_E_NOT_SUPPORT;

            break;

        case CTC_PORT_DIR_PROP_ACL_TCAM_LKUP_TYPE_0:
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(DsDestPortAclCtl_t, DsDestPortAclCtl_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_lkup_type));
            }
            else
            {
                cmd = DRV_IOR(DsDestPort_t, DsDestPort_gAcl_0_aclLookupType_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &acl_lkup_type));
            }
            *p_value = sys_usw_unmap_acl_tcam_lkup_type(lchip, acl_lkup_type);
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_ACL_PORT_BITMAP_ID:
            cmd = DRV_FROM_AT(lchip)
                    ? DRV_IOR(DsDestPortAclCtl_t, DsDestPortAclCtl_aclPortNum_f)
                    : DRV_IOR(DsDestPort_t, DsDestPort_aclPortNum_f);
            break;

/********** ACL property end **********/
        case CTC_PORT_DIR_PROP_QOS_DOMAIN:
            {
                uint32 value1=0;
                uint32 value2=0;

                cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_cosPhbPtr_f):DRV_IOR(DsDestPort_t, DsDestPort_cosPhbPtr_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value1));

                cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dscpPhbPtr_f):DRV_IOR(DsDestPort_t, DsDestPort_dscpPhbPtr_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, &value2));
                if(value1 == value2)
                {
                    *p_value = value1;
                }
                else
                {
                    *p_value =0;
                }
                cmd = 0;
                break;
            }

        case CTC_PORT_DIR_PROP_QOS_COS_DOMAIN:
            cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_cosPhbPtr_f):DRV_IOR(DsDestPort_t, DsDestPort_cosPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_QOS_DSCP_DOMAIN:
            cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_dscpPhbPtr_f):DRV_IOR(DsDestPort_t, DsDestPort_dscpPhbPtr_f);
            break;

        case CTC_PORT_DIR_PROP_DOT1AE_EN:
            if (DRV_FROM_TMM(lchip))
            {
                bind_sc.type = 0;
                bind_sc.gport = gport;
                bind_sc.dir = 0; /* CTC_DOT1AE_SC_DIR_TX */
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                if (MCHIP_1AE(lchip)->get_en_sec_chan)
                {
                    CTC_ERROR_RETURN(MCHIP_1AE(lchip)->get_en_sec_chan(lchip, &bind_sc));
                }
                else
                {
                    return CTC_E_NOT_SUPPORT;
                }
                *p_value = bind_sc.enable;
                cmd = 0;
            }
            else
            {
                cmd = DRV_IOR(DsDestPort_t, DsDestPort_dot1AeEn_f);
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_CHAN_ID:
            {
                bind_sc.type = 0;
                bind_sc.gport = gport;
                bind_sc.dir = 0; /* CTC_DOT1AE_SC_DIR_TX */
                bind_sc.p_chan_id = mem_malloc(MEM_PORT_MODULE,  MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM)*sizeof(uint32));
                if (NULL == bind_sc.p_chan_id)
                {
                    return CTC_E_NO_MEMORY;
                }
                sal_memset(bind_sc.p_chan_id, 0,MCHIP_CAP(SYS_CAP_DOT1AE_SEC_CHAN_NUM)*sizeof(uint32));
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                ret = SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_GET_BIND_SEC_CHAN, lchip, &bind_sc);
                if (ret < 0)
                {
                    mem_free(bind_sc.p_chan_id);
                    return ret;
                }
                if (bind_sc.SecYP2MP)
                {
                    sal_memcpy(p_value, bind_sc.p_chan_id, sizeof(uint32)*MCHIP_CAP(SYS_CAP_DOT1AE_RX_CHAN_NUM));
                }
                else
                {
                    *p_value = bind_sc.p_chan_id[0];
                }
                mem_free(bind_sc.p_chan_id);
                cmd = 0;
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_HASH_TYPE:
            {
                sys_com_dot1ae_hash_type_t hash_type;
                sal_memset(&hash_type, 0, sizeof(sys_com_dot1ae_hash_type_t));
                hash_type.is_set = 0;
                hash_type.dir = 1;
                hash_type.gport = gport;
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_SET_HASH_TYPE, lchip, &hash_type));
                *p_value = hash_type.type;
            }
            break;
        case CTC_PORT_DIR_PROP_DOT1AE_STATS:
            {
                if (!DRV_FROM_TMM(lchip))
                {
                    return CTC_E_NOT_SUPPORT;
                }
                SYS_MAP_GPORT_TO_LCHIP1(gport,lchip);
                CTC_ERROR_RETURN(SYS_CB_RET(CTC_E_NOT_INIT, SYS_CB_DOT1AE_GET_SECY_STATS, lchip, gport, !dir, p_secy_stats));
            }
            break;
        case CTC_PORT_DIR_PROP_SD_ACTION :
            ret = _sys_usw_port_get_sd_action(lchip, CTC_EGRESS, index, p_value);
            cmd = 0;
        break;

        case  CTC_PORT_DIR_PROP_MAX_FRAME_SIZE:
            {
                uint32 tmp_val = 0;
                uint32 max_frame = 0;
                uint32 mac_id = 0;

                if (!(SYS_DMPS_NETWORK_PORT == sys_usw_is_network_port(lchip, gport)))
                {
                    return CTC_E_INVALID_PORT;
                }

                if (DRV_FROM_AT(lchip))
                {
                    uint32 pp_id = 0;
                    uint32 dp_id = 0;
                    uint32 sub_chan = 0;
                    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SUB_CHAN_ID, &sub_chan));
                    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_DP_ID, &dp_id));
                    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
                    cmd = DRV_IOR(NetTxMaxMinLenCfg_t, NetTxMaxMinLenCfg_cfgMaxPktLen_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(SYS_PP_BASE(lchip) + pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), p_value));
                    cmd = 0;
                }
                else if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
                {
                    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, &mac_id));
                    cmd = DRV_IOR(NetTxMaxMinLenCfg_t, NetTxMaxMinLenCfg_cfgMaxPktLen_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, mac_id, cmd, p_value));
                    cmd = 0;
                }
                else
                {
                    cmd = DRV_IOR(NetTxMaxMinLenPortMap_t, NetTxMaxMinLenPortMap_maxLenPortSel_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &tmp_val));
                    cmd = DRV_IOR(NetTxMaxLenCfg_t, NetTxMaxLenCfg_maxCheckLen_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, tmp_val, cmd, &max_frame));
                    *p_value = max_frame;
                    cmd = 0;
                }
            }
            break;
        case CTC_PORT_DIR_PROP_MAC_EN:
            ret = sys_usw_dmps_get_direction_property(lchip, gport, port_prop, CTC_EGRESS, p_value);
            break;
        case CTC_PORT_DIR_PROP_VLAN_DOMAIN:
            cmd = is_support_glb_port ? DRV_IOR(DsGlbDestPort_t, DsGlbDestPort_cvlanSpace_f):
                  DRV_IOR(DsDestPort_t, DsDestPort_cvlanSpace_f);
            break;
        case CTC_PORT_DIR_PROP_PTP_RESIDENCE_TIME_MODE:
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_dstIsPtpNewNode_f);
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &index));
            break;
        case CTC_PORT_DIR_PROP_FLOW_LKUP_BY_OUTER_HEAD:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_aclQosUseInnerInfo_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, p_value));
            *p_value = !(*p_value);
            cmd = 0;
            break;
        case CTC_PORT_DIR_PROP_AWARE_TUNNEL_INFO_EN:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_aclKeyMergeInnerAndOuterHdr_f);
            index = lport;
            break;
        case CTC_PORT_DIR_PROP_CID:
           cmd = DRV_IOR(DsDestPort_t, DsDestPort_categoryId_f);
           index = lport;
           break;
        default:
            return CTC_E_INVALID_PARAM;
        }
    }

    CTC_ERROR_RETURN(ret);

    if (cmd)
    {
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, index, cmd, p_value));
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_internal_property(uint8 lchip, uint32 gport, sys_port_internal_property_t port_prop, uint32 value)
{
    uint8  idx = 0;
    uint8  num = 1;

    uint16 lport = 0;
    uint32 cmd[2] = {0};
    uint32 tmp_value;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port internal property, gport:0x%04X, property:%d, value:%d\n", \
                     gport, port_prop, value);

    /*Sanity check*/
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    switch (port_prop)
    {
    case SYS_PORT_PROP_DEFAULT_PCP:
        cmd[0] = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultPcp_f);
        break;

    case SYS_PORT_PROP_DEFAULT_DEI:
        cmd[0] = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_defaultDei_f);
        break;

    case SYS_PORT_PROP_OAM_TUNNEL_EN:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_oamTunnelEn_f);
        break;

    case SYS_PORT_PROP_OAM_VALID:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_etherOamValid_f);
        value = (value) ? 1 : 0;
        cmd[1] = DRV_IOW(DsDestPort_t, DsDestPort_etherOamValid_f);
        num++;
        break;

    case SYS_PORT_PROP_DISCARD_NONE_8023OAM_EN:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_discardNon8023Oam_f);
        break;

    case SYS_PORT_PROP_REPLACE_TAG_EN:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_defaultReplaceTagEn_f);
        break;

    case SYS_PORT_PROP_EXCEPTION_EN:
        cmd[0] = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_exception2En_f);
        break;

    case SYS_PORT_PROP_EXCEPTION_DISCARD:
        cmd[0] = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_exception2Discard_f);
        break;

    case SYS_PORT_PROP_SECURITY_EXCP_EN:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portSecurityExceptionEn_f);
        break;

    case SYS_PORT_PROP_SECURITY_EN:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portSecurityEn_f);
        break;

    case SYS_PORT_PROP_MAC_SECURITY_DISCARD:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_macSecurityDiscard_f);
        break;
    case SYS_PORT_PROP_REPLACE_DSCP_EN:
        cmd[0] = 0;
        break;
    case SYS_PORT_PROP_STMCTL_EN:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portStormCtlEn_f);
        break;

    case SYS_PORT_PROP_STMCTL_OFFSET:
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portStormCtlPtr_f);
        break;

    /*new properties for GB*/
    case SYS_PORT_PROP_LINK_OAM_EN:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_linkOamEn_f);
        cmd[1] = DRV_IOW(DsDestPort_t, DsDestPort_linkOamEn_f);
        num++;
        break;

    case SYS_PORT_PROP_LINK_OAM_MEP_INDEX:
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_linkOamMepIndex_f);
        break;

    case SYS_PORT_PROP_DOT1AE_TX_SCI_EN:
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_dot1AeSciEn_f);
        break;

    case SYS_PORT_PROP_MAC_AUTH_EN:
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portAuthEn_f);
        cmd[1] = DRV_IOW(DsSrcPort_t, DsSrcPort_portAuthExceptionEn_f);
        num++;
        break;
    case SYS_PORT_PROP_LINK_OAM_LEVEL:
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_linkOamLevel_f);
        cmd[1] = DRV_IOW(DsDestPort_t, DsDestPort_linkOamLevel_f);
        num++;
        break;
    case SYS_PORT_PROP_OAM_MIP_EN:
        value = (value)&0xff;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_mipEn_f);
        cmd[1] = DRV_IOW(DsDestPort_t, DsDestPort_mipEn_f);
        num++;
        break;
    case SYS_PORT_PROP_INGRESS_POLICER_EN:
        value = value ? 1 : 0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portPolicerEn_f);
        break;
    case SYS_PORT_PROP_EGRESS_POLICER_EN:
        value = value ? 1 : 0;
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_portPolicerEn_f);
        break;
    case SYS_PORT_PROP_INGRESS_POLICER_PTR:
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portPolicerPtr_f);
        break;
    case SYS_PORT_PROP_EGRESS_POLICER_PTR:
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_portPolicerPtr_f);
        break;
    case SYS_PORT_PROP_INGRESS_POLICER_LEVEL:
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portPolicerSel_f);
        break;
    case SYS_PORT_PROP_EGRESS_POLICER_LEVEL:
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_portPolicerSel_f);
        break;
    case SYS_PORT_PROP_MICRO_BFD_EN:
        cmd[0] = DRV_IOW(DsPhyPort_t, DsPhyPort_microBfdEn_f);
        break;
    case SYS_PORT_PROP_ETH_TO_CPU_ILOOP_EN:
        tmp_value = value ? 1:0;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_portCrossConnect_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd[0], &tmp_value));
        cmd[0] = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_u1_g2_dsFwdPtr_f);
        break;
    case SYS_PORT_PROP_FLEX_DST_ISOLATEGRP_SEL:
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_cFlexDstIsolateGroupSel_f);
        break;
    case SYS_PORT_PROP_MUX_PORT_TYPE:
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_muxPortType_f);
        break;
    case SYS_PORT_PROP_EVB_LOCAL_PHY_PORT_VALID:
        tmp_value = value ? 1:0;
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_evbDefaultLocalPhyPortValid_f);
        break;
    case SYS_PORT_PROP_VLAN_OPERATION_DIS:
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_ctagOperationDisable_f);
        cmd[1] = DRV_IOW(DsDestPort_t, DsDestPort_stagOperationDisable_f);
        num++;
        break;
    case SYS_PORT_PROP_UNTAG_DEF_VLAN_EN:
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_untagDefaultVlanId_f);
        break;
    case SYS_PORT_PROP_STP_CHECK_EN:
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_stpCheckEn_f);
        break;
    case SYS_PORT_PROP_STP_EN:
        value = (value) ? 0 : 1;
        cmd[0] = DRV_IOW(DsSrcPort_t, DsSrcPort_stpDisable_f);
        break;
    case SYS_PORT_PROP_DEST_L3IF_ID:
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_portMappedInterfaceId_f);
        break;
    case SYS_PORT_PROP_LOGIC_PORT_TYPE_EN:
        value = (value) ? 1 : 0;
        cmd[0] = DRV_IOW(DsDestPort_t, DsDestPort_logicPortType_f);
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    for (idx = 0; idx < num; idx++)
    {
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd[idx], &value));
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_get_internal_property(uint8 lchip, uint32 gport, sys_port_internal_property_t port_prop, uint32* p_value)
{
    uint32 cmd = 0;

    uint16 lport = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port internal property, gport:0x%04X, property:%d!\n", gport, port_prop);

    CTC_PTR_VALID_CHECK(p_value);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    /* zero value */
    *p_value = 0;

    switch (port_prop)
    {
    case SYS_PORT_PROP_DEFAULT_DEI:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_defaultDei_f);
        break;

    case SYS_PORT_PROP_OAM_TUNNEL_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_oamTunnelEn_f);
        break;

    case SYS_PORT_PROP_OAM_VALID:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_etherOamValid_f);
        break;

    case SYS_PORT_PROP_REPLACE_TAG_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_defaultReplaceTagEn_f);
        break;

    case SYS_PORT_PROP_EXCEPTION_EN:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_exception2En_f);
        break;

    case SYS_PORT_PROP_EXCEPTION_DISCARD:
        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_exception2Discard_f);
        break;

    case SYS_PORT_PROP_SECURITY_EXCP_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portSecurityExceptionEn_f);
        break;

    case SYS_PORT_PROP_SECURITY_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portSecurityEn_f);
        break;

    case SYS_PORT_PROP_MAC_SECURITY_DISCARD:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_macSecurityDiscard_f);
        break;
    case SYS_PORT_PROP_REPLACE_DSCP_EN:
        cmd = 0;
        break;
    case SYS_PORT_PROP_STMCTL_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portStormCtlEn_f);
        break;
    case SYS_PORT_PROP_STMCTL_OFFSET:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portStormCtlPtr_f);
        break;

    /*new properties for GB*/
    case SYS_PORT_PROP_LINK_OAM_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_linkOamEn_f);
        break;

    case SYS_PORT_PROP_LINK_OAM_MEP_INDEX:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_linkOamMepIndex_f);
        break;

    case SYS_PORT_PROP_DOT1AE_TX_SCI_EN:
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_dot1AeSciEn_f);
        break;

    case SYS_PORT_PROP_MAC_AUTH_EN:
        cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_portAuthEn_f);
        break;
    case SYS_PORT_PROP_MUX_PORT_TYPE:
        cmd = DRV_IOR(DsDestPort_t, DsDestPort_muxPortType_f);
	    break;

    default:
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, p_value));

    return CTC_E_NONE;
}

int32
sys_usw_port_set_internal_direction_property(uint8 lchip, uint32 gport, sys_port_internal_direction_property_t port_prop, ctc_direction_t dir, uint32 value)
{
    uint16 lport = 0;
    uint32 cmd = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Set port internal property with direction, gport:0x%04X, property:%d, dir:%d,\
                                              value:%d\n", gport, port_prop, dir, value);

    CTC_MAX_VALUE_CHECK(dir, CTC_BOTH_DIRECTION);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    /*do write*/
    if ((CTC_INGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        switch (port_prop)
        {
        case SYS_PORT_DIR_PROP_L2_SPAN_EN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_l2SpanEn_f);
            break;

        case SYS_PORT_DIR_PROP_L2_SPAN_ID:
            if (value > 3)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_l2SpanId_f);
            break;

        case SYS_PORT_DIR_PROP_ETHER_OAM_EDGE_PORT:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_etherOamEdgePort_f);
            break;

        case SYS_PORT_DIR_PROP_ETHER_OAM_LOCK_EN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_etherLckLkupValid_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_TYPE:
            if (value > 3)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_linkLmType_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_COS:
            if (value > 7)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_linkLmCos_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_COS_TYPE:
            if (value > 3)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_linkLmCosType_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_INDEX_BASE:
            if (value > 2047)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_linkLmIndexBase_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LOCK:
             value = value ? 1 : 0;
             cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_linkLckSta_f);
             break;

        case SYS_PORT_DIR_PROP_ETHER_LM_VALID:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_etherLmValid_f);
            break;

        case SYS_PORT_DIR_PROP_MPLS_SECTION_LM_EN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_mplsSectionLmEn_f);
            break;

        case SYS_PORT_DIR_PROP_MPLS_SECTION_LOCK_EN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_mplsSectionLckEn_f);
            break;

        case SYS_PORT_DIR_PROP_DOT1AE_SA_IDX_BASE:
            if (value > (32 - 1))
            {
                return CTC_E_INVALID_PARAM;
            }
            value = value << 2;
            cmd = DRV_IOW(DsPhyPort_t, DsPhyPort_dot1AeSaIndex_f);
            break;
        case SYS_PORT_DIR_PROP_OAM_VALID:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_etherOamValid_f);
            break;
        default:
            return CTC_E_INVALID_PARAM;

        }

        if (cmd)
        {
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        }
    }

    if ((CTC_EGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        switch (port_prop)
        {
        case SYS_PORT_DIR_PROP_L2_SPAN_EN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_l2SpanEn_f);
            break;

        case SYS_PORT_DIR_PROP_L2_SPAN_ID:
            if (value > 3)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_l2SpanId_f);
            break;

        case SYS_PORT_DIR_PROP_ETHER_OAM_EDGE_PORT:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_etherOamEdgePort_f);
            break;

        case SYS_PORT_DIR_PROP_ETHER_OAM_LOCK_EN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_etherLckLkupValid_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_TYPE:
            if (value > 3)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_linkLmType_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_COS:
            if (value > 7)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_linkLmCos_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_COS_TYPE:
            if (value > 3)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_linkLmCosType_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_INDEX_BASE:
            if (value > 2047)
            {
                return CTC_E_INVALID_PARAM;
            }
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_linkLmIndexBase_f);
            break;
        case SYS_PORT_DIR_PROP_LINK_LOCK:
             value = value ? 1 : 0;
             cmd = DRV_IOW(DsDestPort_t, DsDestPort_linkLckSta_f);
             break;

        case SYS_PORT_DIR_PROP_ETHER_LM_VALID:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_etherLmValid_f);
            break;

        case SYS_PORT_DIR_PROP_MPLS_SECTION_LM_EN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_mplsSectionLmEn_f);
            break;

        case SYS_PORT_DIR_PROP_MPLS_SECTION_LOCK_EN:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_mplsSectionLckEn_f);
            break;

        case SYS_PORT_DIR_PROP_DOT1AE_SA_IDX_BASE:
            if (value > (32 - 1))
            {
                return CTC_E_INVALID_PARAM;
            }
            value = value << 2;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_dot1AeSaIndex_f);
            break;
        case SYS_PORT_DIR_PROP_OAM_VALID:
            value = value ? 1 : 0;
            cmd = DRV_IOW(DsDestPort_t, DsDestPort_etherOamValid_f);
            break;
        default:
            return CTC_E_INVALID_PARAM;
        }

        if (cmd)
        {
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &value));
        }
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_get_internal_direction_property(uint8 lchip, uint32 gport, sys_port_internal_direction_property_t port_prop, ctc_direction_t dir, uint32* p_value)
{
    uint16 lport = 0;
    uint32 cmd = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "Get port internal property with direction, gport:0x%04X, property:%d, dir:%d" \
                     , gport, port_prop, dir);

    CTC_PTR_VALID_CHECK(p_value);
    CTC_MAX_VALUE_CHECK(dir, CTC_BOTH_DIRECTION - 1);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    /* zero value */
    *p_value = 0;

    /*do read,only get value by CTC_INGRESS or CTC_EGRESS,no CTC_BOTH_DIRECTION*/
    if (CTC_INGRESS == dir)
    {
        switch (port_prop)
        {
        case SYS_PORT_DIR_PROP_L2_SPAN_EN:
            cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_l2SpanEn_f);
            break;

        case SYS_PORT_DIR_PROP_L2_SPAN_ID:
            cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_l2SpanId_f);
            break;

#if 0
        case SYS_PORT_DIR_PROP_ETHER_OAM_EDGE_PORT:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_etherOamEdgePort_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_TYPE:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_linkLmType_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_COS:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_linkLmCos_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_COS_TYPE:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_linkLmCosType_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_INDEX_BASE:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_linkLmIndexBase_f);
            break;

        case SYS_PORT_DIR_PROP_ETHER_LM_VALID:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_etherLmValid_f);
            break;

        case SYS_PORT_DIR_PROP_MPLS_SECTION_LM_EN:
            cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_mplsSectionLmEn_f);
            break;

        case SYS_PORT_DIR_PROP_MPLS_SECTION_LOCK_EN:
              cmd = DRV_IOR(DsSrcPort_t, DsSrcPort_mplsSectionLckEn_f);
              break;
#endif

        default:
            return CTC_E_INVALID_PARAM;

        }
    }
    else
    {
        switch (port_prop)
        {
        case SYS_PORT_DIR_PROP_L2_SPAN_EN:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_l2SpanEn_f);
            break;

        case SYS_PORT_DIR_PROP_L2_SPAN_ID:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_l2SpanId_f);
            break;

#if 0
        case SYS_PORT_DIR_PROP_ETHER_OAM_EDGE_PORT:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_etherOamEdgePort_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_TYPE:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_linkLmType_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_COS:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_linkLmCos_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_COS_TYPE:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_linkLmCosType_f);
            break;

        case SYS_PORT_DIR_PROP_LINK_LM_INDEX_BASE:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_linkLmIndexBase_f);
            break;

        case SYS_PORT_DIR_PROP_ETHER_LM_VALID:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_etherLmValid_f);
            break;

        case SYS_PORT_DIR_PROP_MPLS_SECTION_LM_EN:
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_mplsSectionLmEn_f);
            break;

        case SYS_PORT_DIR_PROP_MPLS_SECTION_LOCK_EN:
              cmd = DRV_IOR(DsDestPort_t, DsDestPort_mplsSectionLckEn_f);
            break;
#endif

        default:
            return CTC_E_INVALID_PARAM;
        }
    }

    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, p_value));

    return CTC_E_NONE;
}

int32
sys_usw_port_set_port_mac(uint8 lchip, uint32 gport, mac_addr_t mac_da)
{
    uint32 cmd                     = 0;
    int32 ret = CTC_E_NONE;
    uint32 lport                   = 0;
    hw_mac_addr_t mac;
    mac_addr_t cmp_mac_da = {0};
    DsEgressPortMac_m        dsportmac;

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    SYS_USW_SET_HW_MAC(mac,  mac_da);
    SetDsEgressPortMac(A, portMac_f, &dsportmac, mac);
    cmd = DRV_IOW(DsEgressPortMac_t, DRV_ENTRY_FLAG);
    ret = DRV_IOCTL(lchip, lport, cmd, &dsportmac);
    if (ret)
    {
        return ret;
    }
    p_usw_port_master[lchip]->port_prop[lport].is_mac_da = sal_memcmp(mac_da, cmp_mac_da, sizeof(mac_addr_t))? 1: 0;
    SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP, 1);

    return ret;
}

int32
sys_usw_port_set_ipg_size(uint8 lchip, ctc_ipg_size_t index, uint8 size)
{
    uint32 cmd_i = 0;
    uint32 cmd_e = 0;
    uint32 field_val = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "ipg size index:%d ipg size:%d\n", index, size);

    field_val = size;

    switch (index)
    {
    case CTC_IPG_SIZE_0:
        cmd_i = DRV_IOW(IpeIpgCtl_t, IpeIpgCtl_array_0_ipg_f);
        cmd_e = DRV_IOW(EpeIpgCtl_t, EpeIpgCtl_array_0_ipg_f);
        break;

    case CTC_IPG_SIZE_1:
        cmd_i = DRV_IOW(IpeIpgCtl_t, IpeIpgCtl_array_1_ipg_f);
        cmd_e = DRV_IOW(EpeIpgCtl_t, EpeIpgCtl_array_1_ipg_f);
        break;

    case CTC_IPG_SIZE_2:
        cmd_i = DRV_IOW(IpeIpgCtl_t, IpeIpgCtl_array_2_ipg_f);
        cmd_e = DRV_IOW(EpeIpgCtl_t, EpeIpgCtl_array_2_ipg_f);
        break;

    case CTC_IPG_SIZE_3:
        cmd_i = DRV_IOW(IpeIpgCtl_t, IpeIpgCtl_array_3_ipg_f);
        cmd_e = DRV_IOW(EpeIpgCtl_t, EpeIpgCtl_array_3_ipg_f);
        break;

    default:
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd_i, &field_val));
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd_e, &field_val));

    return CTC_E_NONE;
}

int32
sys_usw_port_get_ipg_size(uint8 lchip, ctc_ipg_size_t index, uint8* p_size)
{
    uint32 cmd = 0;
    uint32 field_val = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "ipg size index:%d\n", index);

    switch (index)
    {
    case CTC_IPG_SIZE_0:
        cmd = DRV_IOR(IpeIpgCtl_t, IpeIpgCtl_array_0_ipg_f);
        break;

    case CTC_IPG_SIZE_1:
        cmd = DRV_IOR(IpeIpgCtl_t, IpeIpgCtl_array_1_ipg_f);
        break;

    case CTC_IPG_SIZE_2:
        cmd = DRV_IOR(IpeIpgCtl_t, IpeIpgCtl_array_2_ipg_f);
        break;

    case CTC_IPG_SIZE_3:
        cmd = DRV_IOR(IpeIpgCtl_t, IpeIpgCtl_array_3_ipg_f);
        break;

    default:
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    *p_size = field_val;

    return CTC_E_NONE;
}

int32
sys_usw_port_set_port_mac_postfix(uint8 lchip, uint32 gport, ctc_port_mac_postfix_t* p_port_mac)
{

    uint16 lport     = 0;
    uint32 cmd       = 0;
    uint32 field_val = 0;
    uint32 mac_id    = 0;
    uint32 tbl_id    = 0;
    uint8  step      = 0;
    Sgmac0TxPauseCfg0_m tx_pause_cfg;
    QuadSgmacCfg0_m mac_cfg;
    DsPhyPort_m ds_phy_port;
    DsPortProperty_m ds_port_property;
    DsEgressPortMac_m ds_egress_port_mac;
    hw_mac_addr_t mac;
    hw_mac_addr_t pause_mac;
    uint16 profile_idx = 0;
    uint32 port_type = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    ds_t   ds;
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    if (CTC_PORT_MAC_PREFIX_48BIT != p_port_mac->prefix_type)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " API or some feature is not supported \n");
        return CTC_E_NOT_SUPPORT;
    }

    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type));
    if ((SYS_DMPS_NETWORK_PORT != port_type) && (SYS_DMPS_CPUMAC_NETWORK_PORT != port_type))
    {
        return CTC_E_INVALID_PORT;
    }
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_STATS_ID, (void *)&mac_id));

    SYS_USW_SET_HW_MAC(mac, p_port_mac->port_mac);
    SYS_USW_SET_HW_MAC(pause_mac, p_port_mac->port_mac);

    sal_memset(&ds_phy_port, 0, sizeof(DsPhyPort_m));
    sal_memset(&ds, 0, sizeof(ds));
    cmd = DRV_IOR(DsPhyPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port));
    SetDsPhyPort(A, portMac_f, &ds_phy_port,  mac);
    cmd = DRV_IOW(DsPhyPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port));

    sal_memset(&ds_port_property, 0, sizeof(ds_port_property));
    cmd = DRV_IOR(DsPortProperty_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_port_property));
    SetDsPortProperty(A, macSaByte_f, &ds_port_property,  mac);
    cmd = DRV_IOW(DsPortProperty_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_port_property));

    if(DRV_FROM_TMM(lchip))
    {
        if (mac_id >= SYS_CPU_MAC_ID_MIN && mac_id <= SYS_CPU_MAC_ID_MAX)
        {
            step = (Sgmac1RxPauseCfg_t - Sgmac0RxPauseCfg_t) * (mac_id - SYS_CPU_MAC_ID_MIN);
            cmd = DRV_IOR(Sgmac0TxPauseCfg_t + step, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            field_val = pause_mac[0]&0xFF;
            SetSgmac0TxPauseCfg(V, cfgSgmac0TxPauseMacSaLo_f, &ds, field_val);
            cmd = DRV_IOW(Sgmac0TxPauseCfg_t + step, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

            pause_mac[0] = (pause_mac[1]&0xFF) << 24 | pause_mac[0] >> 8;
            pause_mac[1] = pause_mac[1] >> 8;
            cmd = DRV_IOR(QuadSgmacCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            SetQuadSgmacCfg(A, cfgSgmacTxPauseMacSaHi_f, &ds, pause_mac);
            cmd = DRV_IOW(QuadSgmacCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        }
        else
        {
            if (DRV_FROM_AT(lchip))
            {
                uint8 index = 0;
                McMacPauseTxCtl_m mac_pause_tx_ctl;
                sal_memset(&mac_pause_tx_ctl, 0, sizeof(mac_pause_tx_ctl));
                mac_id = mac_id % 160;/* 160 mac per core in Arctic */
                index = mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM);
                step = (McMacPauseTxCtl_mcMacPauseTxCfg_1_cfgMcMacTxPauseMacSaLo_f - McMacPauseTxCtl_mcMacPauseTxCfg_0_cfgMcMacTxPauseMacSaLo_f)
                        * (mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM));

                pause_mac[1] = mac[1] & 0xFFFF;
                cmd = DRV_IOR(McMacPauseTxCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_pause_tx_ctl));
                SetMcMacPauseTxCtl(V, mcMacPauseTxCfg_0_cfgMcMacTxPauseMacSaLo_f + step, &mac_pause_tx_ctl,  pause_mac[0]);
                SetMcMacPauseTxCtl(V, mcMacPauseTxCfg_0_cfgMcMacTxPauseMacSaHi_f + step, &mac_pause_tx_ctl,  pause_mac[1]);
                cmd = DRV_IOW(McMacPauseTxCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_pause_tx_ctl));
            }
            else
            {
                uint8 index = 0;
                McMacPauseTxCtl1_m mac_pause_tx_ctl;
                sal_memset(&mac_pause_tx_ctl, 0, sizeof(mac_pause_tx_ctl));
                index = mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM);
                step = (McMacPauseTxCtl1_mcMacPauseTxCfg_1_cfgMcMacTxPauseMacSaLo_f - McMacPauseTxCtl1_mcMacPauseTxCfg_0_cfgMcMacTxPauseMacSaLo_f)
                        * (mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM));

                pause_mac[1] = mac[1] & 0xFFFF;
                cmd = DRV_IOR(McMacPauseTxCtl1_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_pause_tx_ctl));
                SetMcMacPauseTxCtl1(V, mcMacPauseTxCfg_0_cfgMcMacTxPauseMacSaLo_f + step, &mac_pause_tx_ctl,  pause_mac[0]);
                SetMcMacPauseTxCtl1(V, mcMacPauseTxCfg_0_cfgMcMacTxPauseMacSaHi_f + step, &mac_pause_tx_ctl,  pause_mac[1]);
                cmd = DRV_IOW(McMacPauseTxCtl1_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &mac_pause_tx_ctl));
            }
        }
    }
    else
    {

        sal_memset(&tx_pause_cfg, 0, sizeof(Sgmac0TxPauseCfg0_m));
        sal_memset(&mac_cfg, 0, sizeof(QuadSgmacCfg0_m));

        step = Sgmac1TxPauseCfg0_t - Sgmac0TxPauseCfg0_t;
        tbl_id = Sgmac0TxPauseCfg0_t + (mac_id / 4) + ((mac_id % 4)*step);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &tx_pause_cfg));
        field_val = pause_mac[0]&0xFF;
        SetSgmac0TxPauseCfg0(V, cfgSgmac0TxPauseMacSaLo_f, &tx_pause_cfg, field_val);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &tx_pause_cfg));

        pause_mac[0] = (pause_mac[1]&0xFF) << 24 | pause_mac[0] >> 8;
        pause_mac[1] = pause_mac[1] >> 8;
        tbl_id = QuadSgmacCfg0_t + (mac_id / 4);
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));
        SetQuadSgmacCfg0(A, cfgSgmacTxPauseMacSaHi_f, &mac_cfg, pause_mac);
        cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mac_cfg));
    }
    if (!p_usw_port_master[lchip]->port_prop[lport].is_mac_da)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "port %u is ecmp interface member, don't support cfg egress port mac\n", gport);
        sal_memset(&ds_egress_port_mac, 0, sizeof(ds_egress_port_mac));
        cmd = DRV_IOW(DsEgressPortMac_t, DRV_ENTRY_FLAG);
        SetDsEgressPortMac(A, portMac_f, &ds_egress_port_mac,  mac);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_egress_port_mac));
    }

    cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_globalSrcPort_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));

    /*Notice: DsPortProperty index now is profile id, not port id, 
    for D2 and TM max phy port is 64, temply alloc index0~63 as phy port use; 64~255 as linkagg port use;
    for TMM max phy port is 256, temply alloc index0~256 as phy port use; 256~511 as linkagg port use;
    TM and TMM max linkagg group is 256, TM use for oam max linkagg group is 191.
    AT max linkagg group is 512, AT use for oam max linkagg group is 128
    should be coherence with oam code*/
    if (SYS_DRV_IS_LINKAGG_PORT(field_val))
    {
        profile_idx = DRV_FROM_AT(lchip)?SYS_INTERNAL_PORT_START + CTC_GPORT_LINKAGG_ID(field_val):SYS_PHY_PORT_NUM_PER_SLICE + CTC_GPORT_LINKAGG_ID(field_val);
        cmd = DRV_IOR(DsPortProperty_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, profile_idx, cmd, &ds_port_property));
        SetDsPortProperty(A, macSaByte_f, &ds_port_property,  mac);
        cmd = DRV_IOW(DsPortProperty_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, profile_idx, cmd, &ds_port_property));
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_if_status(uint8 lchip, uint16 lport, uint32 value)
{
    uint32 cmd = 0;
    int32 ret = 0;

    cmd = DRV_IOW(DsPortProperty_t, DsPortProperty_ifStatus_f);
    ret = (DRV_FIELD_IOCTL(lchip, lport, cmd, &value));

    return ret;
}

int32
sys_usw_port_get_port_mac(uint8 lchip, uint32 gport, mac_addr_t* p_port_mac)
{
    uint16 lport = 0;
    uint32 cmd  = 0;
    DsPhyPort_m ds_phy_port;
    hw_mac_addr_t hw_mac;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOR(DsPhyPort_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_phy_port));

    sal_memset(&hw_mac, 0, sizeof(hw_mac_addr_t));
    GetDsPhyPort(A, portMac_f, &ds_phy_port, hw_mac);

    SYS_USW_SET_USER_MAC(*p_port_mac, hw_mac);

    return CTC_E_NONE;
}

STATIC void
_sys_usw_port_scl_type(uint8 lchip, uint8 dir, sys_scl_key_mapping_type_t mapping_type, sys_scl_type_para_t* p_scl_type_para)
{
    uint8 i = 0;

    sys_scl_type_map_t scl_hash_type_map[][CTC_PORT_IGS_SCL_HASH_TYPE_MAX] =
    {
        {
             {0, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_DISABLE),        CTC_PORT_IGS_SCL_HASH_TYPE_DISABLE         },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_DOUBLEVLANPORT), CTC_PORT_IGS_SCL_HASH_TYPE_PORT_2VLAN      },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_SVLANPORT),      CTC_PORT_IGS_SCL_HASH_TYPE_PORT_SVLAN      },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_CVLANPORT),      CTC_PORT_IGS_SCL_HASH_TYPE_PORT_CVLAN      },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_SVLANCOSPORT),   CTC_PORT_IGS_SCL_HASH_TYPE_PORT_SVLAN_COS  },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_CVLANCOSPORT),   CTC_PORT_IGS_SCL_HASH_TYPE_PORT_CVLAN_COS  },
             {1, 0, 1, DRV_ENUM(DRV_USERIDPORTHASHTYPE_MAC),            CTC_PORT_IGS_SCL_HASH_TYPE_MAC_SA          },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_MACPORT),        CTC_PORT_IGS_SCL_HASH_TYPE_PORT_MAC_SA     },
             {1, 1, 1, DRV_ENUM(DRV_USERIDPORTHASHTYPE_MAC),            CTC_PORT_IGS_SCL_HASH_TYPE_MAC_DA          },
             {1, 1, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_MACPORT),        CTC_PORT_IGS_SCL_HASH_TYPE_PORT_MAC_DA     },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_IPSA),           CTC_PORT_IGS_SCL_HASH_TYPE_IP_SA           },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_IPDA),           CTC_PORT_IGS_SCL_HASH_TYPE_IP_DA           },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_IPSAPORT),       CTC_PORT_IGS_SCL_HASH_TYPE_PORT_IP_SA      },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_PORT),           CTC_PORT_IGS_SCL_HASH_TYPE_PORT            },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_NSH),            CTC_PORT_IGS_SCL_HASH_TYPE_NSH             },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_SCLFLOW),        CTC_PORT_IGS_SCL_HASH_TYPE_L2              },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL),         CTC_PORT_IGS_SCL_HASH_TYPE_TUNNEL          },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL),         CTC_PORT_IGS_SCL_HASH_TYPE_TUNNEL_RPF      },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL),         CTC_PORT_IGS_SCL_HASH_TYPE_IPV4_TUNNEL_AUTO},
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL),         CTC_PORT_IGS_SCL_HASH_TYPE_NVGRE           },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL),         CTC_PORT_IGS_SCL_HASH_TYPE_VXLAN           },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_TRILL),          CTC_PORT_IGS_SCL_HASH_TYPE_TRILL           },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_SVLANDSCPPORT),  CTC_PORT_IGS_SCL_HASH_TYPE_PORT_SVLAN_DSCP },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_SVLAN),          CTC_PORT_IGS_SCL_HASH_TYPE_SVLAN           },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_SVLANMACSA),     CTC_PORT_IGS_SCL_HASH_TYPE_SVLAN_MAC       },
             {1, 0, 0, DRV_ENUM(DRV_USERIDPORTHASHTYPE_SCLFLOW),        CTC_PORT_IGS_SCL_HASH_TYPE_UDF             }
        },
        {
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_DISABLE),       CTC_PORT_EGS_SCL_HASH_TYPE_DISABLE         },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_DOUBLEVLANPORT),CTC_PORT_EGS_SCL_HASH_TYPE_PORT_2VLAN      },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_SVLANPORT),     CTC_PORT_EGS_SCL_HASH_TYPE_PORT_SVLAN      },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_CVLANPORT),     CTC_PORT_EGS_SCL_HASH_TYPE_PORT_CVLAN      },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_SVLANCOSPORT),  CTC_PORT_EGS_SCL_HASH_TYPE_PORT_SVLAN_COS  },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_CVLANCOSPORT),  CTC_PORT_EGS_SCL_HASH_TYPE_PORT_CVLAN_COS  },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_PORT),          CTC_PORT_EGS_SCL_HASH_TYPE_PORT            },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_PORTCROSS),     CTC_PORT_EGS_SCL_HASH_TYPE_PORT_XC         },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSXCOAMHASHTYPE_PORTVLANCROSS), CTC_PORT_EGS_SCL_HASH_TYPE_PORT_VLAN_XC    },
            {0, 0, 0, DRV_ENUM(DRV_EGRESSSCLHASHTYPE_METADATADVPGROUP), CTC_PORT_EGS_SCL_HASH_TYPE_MD_ISOLATION_GRP},
            {0, 0, 0, DRV_ENUM(DRV_EGRESSSCLHASHTYPE_FIDDVPGROUP),     CTC_PORT_EGS_SCL_HASH_TYPE_FID_LDP_GRP},
            {0, 0, 0, DRV_ENUM(DRV_EGRESSSCLHASHTYPE_VPPAIR),          CTC_PORT_EGS_SCL_HASH_TYPE_LP_XC},
            {0, 0, 0, DRV_ENUM(DRV_EGRESSSCLHASHTYPE_I2ECIDDVPGROUP),  CTC_PORT_EGS_SCL_HASH_TYPE_LP_GRP},
            {0, 0, 0, 0xF,  CTC_PORT_EGS_SCL_HASH_TYPE_NSH}
        }
    };

    sys_scl_type_map_t scl_tcam_type_map[CTC_PORT_IGS_SCL_TCAM_TYPE_MAX] =
    {
        {0, 0, 0, 0xFF,        CTC_PORT_IGS_SCL_TCAM_TYPE_DISABLE   },
        {1, 0, 1, TCAML2KEY,   CTC_PORT_IGS_SCL_TCAM_TYPE_MAC       },
        {1, 0, 1, TCAML2L3KEY, CTC_PORT_IGS_SCL_TCAM_TYPE_IP        },
        {1, 0, 1, TCAML3KEY,   CTC_PORT_IGS_SCL_TCAM_TYPE_IP_SINGLE },
        {1, 0, 0, TCAML2KEY,   CTC_PORT_IGS_SCL_TCAM_TYPE_VLAN      },
        {1, 0, 0, TCAML2L3KEY,   CTC_PORT_IGS_SCL_TCAM_TYPE_TUNNEL    },
        {1, 0, 0, TCAML2L3KEY,   CTC_PORT_IGS_SCL_TCAM_TYPE_TUNNEL_RPF},
        {1, 0, 0, TCAMUSERIDKEY,   CTC_PORT_IGS_SCL_TCAM_TYPE_RESOLVE_CONFLICT},
        {1, 0, 0, TCAMUDFSHORTKEY, CTC_PORT_IGS_SCL_TCAM_TYPE_UDF},
        {1, 0, 0, TCAMUDFLONGKEY, CTC_PORT_IGS_SCL_TCAM_TYPE_UDF_EXT},
        {1, 0, 0, TCAMUDFQUADKEY, CTC_PORT_IGS_SCL_TCAM_TYPE_UDF_QUAD}
    };

    if (SYS_PORT_KEY_MAPPING_TYPE_DRV2CTC == mapping_type)
    {
        if (CTC_INGRESS == dir)
        {
            p_scl_type_para->ctc_hash_type = CTC_PORT_IGS_SCL_HASH_TYPE_DISABLE;
            if (DRV_ENUM(DRV_USERIDPORTHASHTYPE_DISABLE) == p_scl_type_para->drv_hash_type)
            {
                p_scl_type_para->ctc_hash_type = CTC_PORT_IGS_SCL_HASH_TYPE_DISABLE;
            }
            else if (DRV_ENUM(DRV_USERIDPORTHASHTYPE_TUNNEL) != p_scl_type_para->drv_hash_type)
            {
                for (i = 0; i < CTC_PORT_IGS_SCL_HASH_TYPE_MAX; i++)
                {
                    if ((scl_hash_type_map[CTC_INGRESS][i].drv_type == p_scl_type_para->drv_hash_type)
                        && (DRV_ENUM(DRV_USERIDPORTHASHTYPE_TRILL) == p_scl_type_para->drv_hash_type))
                    {
                        p_scl_type_para->ctc_hash_type = CTC_PORT_IGS_SCL_HASH_TYPE_TRILL;
                    }
                    else if ((scl_hash_type_map[CTC_INGRESS][i].drv_type == p_scl_type_para->drv_hash_type)
                       && (scl_hash_type_map[CTC_INGRESS][i].use_macda == p_scl_type_para->use_macda))
                    {
                        p_scl_type_para->ctc_hash_type = scl_hash_type_map[CTC_INGRESS][i].ctc_type;
                        break;
                    }
                }
            }
            else
            {
                if (p_scl_type_para->tunnel_en)
                {
                    p_scl_type_para->ctc_hash_type = CTC_PORT_IGS_SCL_HASH_TYPE_TUNNEL;
                }

                if (p_scl_type_para->tunnel_en && p_scl_type_para->tunnel_rpf_check)
                {
                    p_scl_type_para->ctc_hash_type = CTC_PORT_IGS_SCL_HASH_TYPE_TUNNEL_RPF;
                }

                if (p_scl_type_para->auto_tunnel)
                {
                    p_scl_type_para->ctc_hash_type = CTC_PORT_IGS_SCL_HASH_TYPE_IPV4_TUNNEL_AUTO;
                }

                if (p_scl_type_para->nvgre_en)
                {
                    p_scl_type_para->ctc_hash_type = CTC_PORT_IGS_SCL_HASH_TYPE_NVGRE;
                }

                if (p_scl_type_para->vxlan_en)
                {
                    p_scl_type_para->ctc_hash_type = CTC_PORT_IGS_SCL_HASH_TYPE_VXLAN;
                }
            }

            if (p_scl_type_para->tcam_en)
            {
                for (i = 0; i < CTC_PORT_IGS_SCL_TCAM_TYPE_MAX; i++)
                {
                    if (scl_tcam_type_map[i].drv_type == p_scl_type_para->drv_tcam_type)
                    {
                        p_scl_type_para->ctc_tcam_type = scl_tcam_type_map[i].ctc_type;
                        break;
                    }
                }
            }
        }
        else if (CTC_EGRESS == dir)
        {
            for (i = 0; i < CTC_PORT_EGS_SCL_HASH_TYPE_MAX; i++)
            {
                if (scl_hash_type_map[CTC_EGRESS][i].drv_type == p_scl_type_para->drv_hash_type)
                {
                    p_scl_type_para->ctc_hash_type = scl_hash_type_map[CTC_EGRESS][i].ctc_type;
                    break;
                }
            }
            p_scl_type_para->drv_tcam_type = CTC_PORT_IGS_SCL_TCAM_TYPE_DISABLE;
        }
    }
    else if (SYS_PORT_KEY_MAPPING_TYPE_CTC2DRV == mapping_type)
    {
        p_scl_type_para->drv_hash_type = scl_hash_type_map[dir][p_scl_type_para->ctc_hash_type].drv_type;

        if (CTC_INGRESS == dir)
        {
            p_scl_type_para->drv_hash_type = scl_hash_type_map[dir][p_scl_type_para->ctc_hash_type].drv_type;
            p_scl_type_para->use_macda = scl_hash_type_map[dir][p_scl_type_para->ctc_hash_type].use_macda;
            p_scl_type_para->vlan_high_priority = scl_hash_type_map[dir][p_scl_type_para->ctc_hash_type].vlan_high_priority;
            if (CTC_PORT_IGS_SCL_TCAM_TYPE_DISABLE == p_scl_type_para->ctc_tcam_type)
            {
                p_scl_type_para->tcam_en = 0;
            }
            else
            {
                p_scl_type_para->tcam_en = 1;
                p_scl_type_para->drv_tcam_type = scl_tcam_type_map[p_scl_type_para->ctc_tcam_type].drv_type;
            }
        }
        else if (CTC_EGRESS == dir)
        {
            p_scl_type_para->drv_hash_type = scl_hash_type_map[dir][p_scl_type_para->ctc_hash_type].drv_type;
            p_scl_type_para->tcam_en = 0;
        }
    }
    return;
}

STATIC int32
_sys_usw_port_unmap_scl_type(uint8 lchip, uint8 dir, sys_scl_type_para_t* p_scl_type_para)
{
    _sys_usw_port_scl_type(lchip, dir, SYS_PORT_KEY_MAPPING_TYPE_DRV2CTC, p_scl_type_para);

    if (CTC_INGRESS == dir)
    {
        CTC_MAX_VALUE_CHECK(p_scl_type_para->ctc_hash_type, CTC_PORT_IGS_SCL_HASH_TYPE_MAX - 1);
        CTC_MAX_VALUE_CHECK(p_scl_type_para->ctc_tcam_type, CTC_PORT_IGS_SCL_TCAM_TYPE_MAX - 1);
    }
    else
    {
        CTC_MAX_VALUE_CHECK(p_scl_type_para->ctc_hash_type, CTC_PORT_EGS_SCL_HASH_TYPE_MAX - 1);
    }
    return CTC_E_NONE;
}

int32
_sys_usw_port_map_scl_type(uint8 lchip, uint8 dir, sys_scl_type_para_t* p_scl_type_para)
{
    if (CTC_INGRESS == dir)
    {
        CTC_MAX_VALUE_CHECK(p_scl_type_para->ctc_hash_type, CTC_PORT_IGS_SCL_HASH_TYPE_MAX - 1);
        CTC_MAX_VALUE_CHECK(p_scl_type_para->ctc_tcam_type, CTC_PORT_IGS_SCL_TCAM_TYPE_MAX - 1);
    }
    else
    {
        CTC_MAX_VALUE_CHECK(p_scl_type_para->ctc_hash_type, CTC_PORT_EGS_SCL_HASH_TYPE_MAX - 1);
    }

    _sys_usw_port_scl_type(lchip, dir, SYS_PORT_KEY_MAPPING_TYPE_CTC2DRV, p_scl_type_para);
    if(p_scl_type_para->ctc_hash_type && p_scl_type_para->drv_hash_type == 0)
    {
        return CTC_E_NOT_SUPPORT;
    }
    if(p_scl_type_para->ctc_tcam_type && p_scl_type_para->drv_tcam_type == 0xFF)
    {
        return CTC_E_NOT_SUPPORT;
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_port_chk_scl_vlan_dscp(uint8 lchip, ctc_port_scl_property_t* p_prop)
{
    uint8 hash_is_vlan_dscp = (CTC_PORT_IGS_SCL_HASH_TYPE_PORT_SVLAN_DSCP == p_prop->hash_type);
    uint8 tcam_is_resolve_conflict = (CTC_PORT_IGS_SCL_TCAM_TYPE_RESOLVE_CONFLICT == p_prop->tcam_type);
    uint8 dir_is_ingress = (CTC_INGRESS == p_prop->direction);

    if (hash_is_vlan_dscp && DRV_IS_DUET2(lchip))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Hash key is not support!\n");
        CTC_ERROR_RETURN(CTC_E_INVALID_CONFIG);
    }
    if (hash_is_vlan_dscp && !dir_is_ingress)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Direction is wrong!\n");
        CTC_ERROR_RETURN(CTC_E_INVALID_CONFIG);
    }
    /*resolve conflict only support ipv4 and ipv6 tcam key*/
    if (hash_is_vlan_dscp && dir_is_ingress && tcam_is_resolve_conflict && DRV_IS_TSINGMA(lchip))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Resolve conflict is not support!\n");
        CTC_ERROR_RETURN(CTC_E_INVALID_CONFIG);
    }
    return CTC_E_NONE;
}

int32
sys_usw_port_set_scl_hash_tcam_priority(uint8 lchip, uint32 gport, uint8 scl_id, uint8 is_tcam, uint8 value)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    DsPhyPortExt_m ds;

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));

    if((scl_id == 0)&&(is_tcam == 0))
    {
        SetDsPhyPortExt(V, hash1Priority_f, &ds, value);
    }
    else if((scl_id == 1)&&(is_tcam == 0))
    {
        SetDsPhyPortExt(V, hash2Priority_f, &ds, value);
    }
    else if((scl_id == 0)&&(is_tcam !=0))
    {
        SetDsPhyPortExt(V, tcam1Priority_f, &ds, value);
    }
    else
    {
        SetDsPhyPortExt(V, tcam2Priority_f, &ds, value);
    }

    cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));

    return CTC_E_NONE;

}

int32
sys_usw_port_set_scl_property(uint8 lchip, uint32 gport, ctc_port_scl_property_t* p_prop)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    uint8 ipv4_tunnel_en = 0;
    uint8 ipv4_gre_tunnel_en = 0;
    uint8 auto_tunnel = 0;
    uint8 v6_tunnel_en = 0;
    uint8 auto_v6_tunnel = 0;
    uint8 v4_vxlan_en = 0;
    uint8 v6_nvgre_en = 0;
    uint8 v6_vxlan_en = 0;
    uint8 rpf_check_en = 0;
    uint8 auto_tunnel_hash1 = 0;
    uint8 auto_v6_tunnel_hash0 = 0;
    uint32 vlan_high_priority = 0;
    sys_scl_type_para_t scl_type_para;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    CTC_PTR_VALID_CHECK(p_prop);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    CTC_MAX_VALUE_CHECK(p_prop->direction, (CTC_BOTH_DIRECTION - 1));
    if (p_prop->class_id_en && p_prop->use_logic_port_en)
    {
        return CTC_E_INVALID_PARAM;
    }
    /*
    add check only scl id 1 support check tunnel rpf;
    tcam big than 1 don't support type resolve hash conflict.
    */
    if ((CTC_PORT_IGS_SCL_HASH_TYPE_TUNNEL_RPF == p_prop->hash_type && 1 != p_prop->scl_id)
        || ((CTC_PORT_IGS_SCL_TCAM_TYPE_RESOLVE_CONFLICT == p_prop->tcam_type)
        && (p_prop->scl_id >= 2)))
    {
        return CTC_E_INVALID_PARAM;
    }

    CTC_ERROR_RETURN(_sys_usw_port_chk_scl_vlan_dscp(lchip, p_prop));

    if (CTC_PORT_IGS_SCL_TCAM_TYPE_DISABLE != p_prop->tcam_type && CTC_EGRESS == p_prop->direction)
    {
        return CTC_E_NOT_SUPPORT;
    }

    if ((CTC_EGRESS == p_prop->direction) && ((0 != p_prop->hash_vlan_range_dis) || (0 != p_prop->tcam_vlan_range_dis)))
    {
        return CTC_E_NOT_SUPPORT;
    }

    /**< [TM] Check hash lookup level */
    if ((CTC_PORT_IGS_SCL_HASH_TYPE_DISABLE != p_prop->hash_type) && \
        (CTC_PORT_EGS_SCL_HASH_TYPE_DISABLE != p_prop->hash_type))
    {
        CTC_MAX_VALUE_CHECK(p_prop->scl_id, 1);
    }

    /*Check tcam lookup level*/
    if (CTC_PORT_IGS_SCL_TCAM_TYPE_DISABLE != p_prop->tcam_type)
    {
        CTC_MAX_VALUE_CHECK(p_prop->scl_id, (MCHIP_CAP(SYS_CAP_SCL_IGS_TCAM_NUM) - 1));
    }
    SYS_USW_MAX_CLASS_ID_CHECK(p_prop->class_id);
    if(p_prop->class_id_en)
    {
        SYS_USW_MIN_CLASS_ID_CHECK(p_prop->class_id);
    }
    sal_memset(&scl_type_para, 0, sizeof(sys_scl_type_para_t));
    scl_type_para.ctc_hash_type = p_prop->hash_type;
    scl_type_para.ctc_tcam_type = p_prop->tcam_type;
    CTC_ERROR_RETURN(_sys_usw_port_map_scl_type(lchip, p_prop->direction, &scl_type_para));

    if (CTC_INGRESS == p_prop->direction)
    {
        DsPhyPortExt_m ds;
        DsPhyPortExt2_m ds2;
        uint32 field_value = 0;

        cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));

        cmd = DRV_IOR(DsPhyPortExt2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds2));
        if (0 == p_prop->scl_id)
        {
            ipv4_tunnel_en = GetDsPhyPortExt(V, ipv4TunnelHashEn1_f, &ds);
            v6_tunnel_en = GetDsPhyPortExt(V, ipv6TunnelHashEn0_f, &ds);
            ipv4_gre_tunnel_en = GetDsPhyPortExt(V, ipv4GreTunnelHashEn1_f, &ds);
            auto_tunnel = GetDsPhyPortExt(V, autoTunnelEn_f, &ds);
            auto_v6_tunnel = GetDsPhyPortExt(V, autoIpv6TunnelEn_f, &ds);
            v4_vxlan_en = GetDsPhyPortExt(V, ipv4VxlanTunnelHashEn1_f, &ds);
            v6_vxlan_en = GetDsPhyPortExt(V, ipv6VxlanTunnelHashEn1_f, &ds);
            v6_nvgre_en = GetDsPhyPortExt(V, ipv6NvgreTunnelHashEn1_f, &ds);
            auto_tunnel_hash1 = GetDsPhyPortExt(V, autoTunnelForHash1_f, &ds);
            auto_v6_tunnel_hash0 = GetDsPhyPortExt(V, autoIpv6TunnelForHash0_f, &ds);
            if (DRV_FROM_TMM(lchip))
            {
                ipv4_tunnel_en = GetDsPhyPortExt2(V, ipv4TunnelHashEn0_f, &ds2);
                v6_tunnel_en = GetDsPhyPortExt2(V, ipv6TunnelHashEn0_f, &ds2);
                ipv4_gre_tunnel_en = GetDsPhyPortExt2(V, ipv4GreTunnelHashEn0_f, &ds2);
                auto_tunnel = GetDsPhyPortExt2(V, autoTunnelEn_f, &ds2);
                auto_v6_tunnel = GetDsPhyPortExt2(V, autoIpv6TunnelEn_f, &ds2);
                v4_vxlan_en = GetDsPhyPortExt2(V, ipv4VxlanTunnelHashEn0_f, &ds2);
                v6_vxlan_en = GetDsPhyPortExt2(V, ipv6VxlanTunnelHashEn0_f, &ds2);
                v6_nvgre_en = GetDsPhyPortExt2(V, ipv6NvgreTunnelHashEn0_f, &ds2);
                auto_tunnel_hash1 = GetDsPhyPortExt2(V, autoTunnelForHash0_f, &ds2);
                auto_v6_tunnel_hash0 = GetDsPhyPortExt2(V, autoIpv6TunnelForHash0_f, &ds2);
            }
        }
        else if(1 == p_prop->scl_id)
        {
            ipv4_tunnel_en = GetDsPhyPortExt(V, ipv4TunnelHashEn2_f, &ds);
            v6_tunnel_en = GetDsPhyPortExt(V, ipv6TunnelHashEn1_f, &ds);
            ipv4_gre_tunnel_en = GetDsPhyPortExt(V, ipv4GreTunnelHashEn2_f, &ds);
            auto_tunnel = GetDsPhyPortExt(V, autoTunnelEn_f, &ds);
            rpf_check_en = GetDsPhyPortExt(V, tunnelRpfCheck_f, &ds);
            auto_v6_tunnel = GetDsPhyPortExt(V, autoIpv6TunnelEn_f, &ds);
            v4_vxlan_en = GetDsPhyPortExt(V, ipv4VxlanTunnelHashEn2_f, &ds);
            v6_nvgre_en = GetDsPhyPortExt(V, ipv6NvgreTunnelHashEn2_f, &ds);
            v6_vxlan_en = GetDsPhyPortExt(V, ipv6VxlanTunnelHashEn2_f, &ds);
            auto_tunnel_hash1 = GetDsPhyPortExt(V, autoTunnelForHash1_f, &ds);
            auto_v6_tunnel_hash0 = GetDsPhyPortExt(V, autoIpv6TunnelForHash0_f, &ds);
            if (DRV_FROM_TMM(lchip))
            {
                ipv4_tunnel_en = GetDsPhyPortExt2(V, ipv4TunnelHashEn1_f, &ds2);
                v6_tunnel_en = GetDsPhyPortExt2(V, ipv6TunnelHashEn1_f, &ds2);
                ipv4_gre_tunnel_en = GetDsPhyPortExt2(V, ipv4GreTunnelHashEn1_f, &ds2);
                auto_tunnel = GetDsPhyPortExt2(V, autoTunnelEn_f, &ds2);
                rpf_check_en = GetDsPhyPortExt2(V, tunnelRpfCheck_f, &ds2);
                auto_v6_tunnel = GetDsPhyPortExt2(V, autoIpv6TunnelEn_f, &ds2);
                v4_vxlan_en = GetDsPhyPortExt2(V, ipv4VxlanTunnelHashEn1_f, &ds2);
                v6_nvgre_en = GetDsPhyPortExt2(V, ipv6NvgreTunnelHashEn1_f, &ds2);
                v6_vxlan_en = GetDsPhyPortExt2(V, ipv6VxlanTunnelHashEn1_f, &ds2);
                auto_tunnel_hash1 = GetDsPhyPortExt2(V, autoTunnelForHash0_f, &ds2);
                auto_v6_tunnel_hash0 = GetDsPhyPortExt2(V, autoIpv6TunnelForHash0_f, &ds2);
            }
        }
        if (CTC_PORT_IGS_SCL_HASH_TYPE_TUNNEL == p_prop->hash_type)
        {
            ipv4_gre_tunnel_en = 1;
            v6_nvgre_en = 1;
            ipv4_tunnel_en = 1;
            v6_tunnel_en = 1;
        }
        else if (CTC_PORT_IGS_SCL_HASH_TYPE_TUNNEL_RPF == p_prop->hash_type)
        {
            ipv4_gre_tunnel_en = 1;
            ipv4_tunnel_en = 1;
            v6_tunnel_en = 1;
            v6_nvgre_en = 1;
            rpf_check_en = 1;
        }
        else if (CTC_PORT_IGS_SCL_HASH_TYPE_IPV4_TUNNEL_AUTO == p_prop->hash_type)
        {
            ipv4_gre_tunnel_en = 1;
            v6_nvgre_en = 1;
            ipv4_tunnel_en = 1;
            v6_tunnel_en = 1;
            auto_tunnel = 1;
            auto_v6_tunnel = 1;
            auto_tunnel_hash1 = (0 == p_prop->scl_id) ? 1 :0;
            auto_v6_tunnel_hash0 = (0 == p_prop->scl_id) ? 1 :0;
        }
        else if (CTC_PORT_IGS_SCL_HASH_TYPE_NVGRE == p_prop->hash_type)
        {
            ipv4_gre_tunnel_en = 1;
            v6_nvgre_en = 1;
        }
        else if (CTC_PORT_IGS_SCL_HASH_TYPE_VXLAN == p_prop->hash_type)
        {
            v4_vxlan_en = 1;
            v6_vxlan_en = 1;
        }
        else if(CTC_PORT_IGS_SCL_HASH_TYPE_DISABLE == p_prop->hash_type)
        {
            ipv4_tunnel_en = 0;
            ipv4_gre_tunnel_en = 0;
            if(0 == p_prop->scl_id)
            {
                auto_tunnel = auto_tunnel_hash1 ? 0 : auto_tunnel;
                auto_v6_tunnel = auto_v6_tunnel_hash0 ? 0 : auto_v6_tunnel;
            }
            if(1 == p_prop->scl_id)
            {
                auto_tunnel = (!auto_tunnel_hash1) ?  0 : auto_tunnel;
                auto_v6_tunnel = (!auto_v6_tunnel_hash0)? 0 : auto_v6_tunnel;
            }

            v6_tunnel_en = 0;
            v4_vxlan_en = 0;
            v6_nvgre_en = 0;
            v6_vxlan_en = 0;
            rpf_check_en = 0;
        }

        /* default entry merge bitmap, for example, merge bmp 0b'0011 --> defaultEntry0Ignore is 0b'1100*/
        if(p_prop->default_merge_bmp || 
                p_prop->class_id == MCHIP_CAP(SYS_CAP_SCL_LABEL_FOR_IPSG) || \
                p_prop->class_id == MCHIP_CAP(SYS_CAP_SCL_LABEL_FOR_VLAN_CLASS) || \
                p_prop->class_id == MCHIP_CAP(SYS_CAP_SCL_LABEL_FOR_SRV6))
        {
            field_value = p_prop->default_merge_bmp;
            CTC_BIT_SET(field_value, p_prop->scl_id);
            field_value = ((1<<MCHIP_CAP(SYS_CAP_SCL_IGS_TCAM_NUM))-1) & (~field_value);
        }

        if (0 == p_prop->scl_id)
        {
            SetDsPhyPortExt(V, userIdPortHash1Type_f, &ds, scl_type_para.drv_hash_type);
            SetDsPhyPortExt(V, hash1UseDa_f, &ds, scl_type_para.use_macda);
            SetDsPhyPortExt(V, userIdTcam1En_f, &ds, scl_type_para.tcam_en);
            SetDsPhyPortExt(V, userIdTcam1Type_f, &ds, scl_type_para.drv_tcam_type);
            SetDsPhyPortExt(V, hashLookup1UseLabel_f , &ds, (p_prop->class_id_en ? 1 : 0));
            SetDsPhyPortExt(V, userIdLabel1_f, &ds, p_prop->class_id);
            SetDsPhyPortExt(V, userId1UseLogicPort_f , &ds, (p_prop->use_logic_port_en ? 1 : 0));
            SetDsPhyPortExt(V, tcamUseLogicPort_f , &ds, (p_prop->use_logic_port_en ? 1 : 0));

            SetDsPhyPortExt(V, ipv4TunnelHashEn1_f, &ds, ipv4_tunnel_en);
            SetDsPhyPortExt(V, ipv6TunnelHashEn0_f, &ds, v6_tunnel_en);
            SetDsPhyPortExt(V, ipv4GreTunnelHashEn1_f, &ds, ipv4_gre_tunnel_en);
            SetDsPhyPortExt(V, autoTunnelEn_f, &ds, auto_tunnel);
            SetDsPhyPortExt(V, autoTunnelForHash1_f, &ds, auto_tunnel_hash1);
            SetDsPhyPortExt(V, autoIpv6TunnelEn_f, &ds, auto_v6_tunnel);
            SetDsPhyPortExt(V, autoIpv6TunnelForHash0_f, &ds, auto_v6_tunnel_hash0);
            SetDsPhyPortExt(V, ipv4VxlanTunnelHashEn1_f, &ds, v4_vxlan_en);
            SetDsPhyPortExt(V, ipv6NvgreTunnelHashEn1_f, &ds, v6_nvgre_en);
            SetDsPhyPortExt(V, ipv6VxlanTunnelHashEn1_f, &ds, v6_vxlan_en);
            /**< [TM] Append hash and tcam vlan range enable */
            SetDsPhyPortExt(V, hash1VlanRangeEn_f, &ds, (p_prop->hash_vlan_range_dis? 0: 1));
            SetDsPhyPortExt(V, tcam1VlanRangeEn_f, &ds, (p_prop->tcam_vlan_range_dis? 0: 1));
            /**< [TM] Append tcam use logic port */
            SetDsPhyPortExt(V, tcam1UseLogicPort_f , &ds, (p_prop->use_logic_port_en ? 1 : 0));
            /**< [TM] Append hash mcast disable */
            SetDsPhyPortExt(V, mcMacDisableHash0_f , &ds, (p_prop->hash_mcast_dis ? 1 : 0));
            SetDsPhyPortExt(V, defaultEntry0Ignore_f, &ds, field_value);
            
            SetDsPhyPortExt2(V, userIdPortHash0Type_f, &ds2, scl_type_para.drv_hash_type);
            SetDsPhyPortExt2(V, hash0UseDa_f, &ds2, scl_type_para.use_macda);
            SetDsPhyPortExt2(V, hashLookup0UseLabel_f , &ds2, (p_prop->class_id_en ? 1 : 0));
            SetDsPhyPortExt2(V, userIdLabel0_f, &ds2, p_prop->class_id);
            SetDsPhyPortExt2(V, userId0UseLogicPort_f , &ds2, (p_prop->use_logic_port_en ? 1 : 0));
            SetDsPhyPortExt2(V, ipv4TunnelHashEn0_f, &ds2, ipv4_tunnel_en);
            SetDsPhyPortExt2(V, ipv6TunnelHashEn0_f, &ds2, v6_tunnel_en);
            SetDsPhyPortExt2(V, ipv4GreTunnelHashEn0_f, &ds2, ipv4_gre_tunnel_en);
            SetDsPhyPortExt2(V, autoTunnelEn_f, &ds2, auto_tunnel);
            SetDsPhyPortExt2(V, autoTunnelForHash0_f, &ds2, auto_tunnel_hash1);
            SetDsPhyPortExt2(V, autoIpv6TunnelEn_f, &ds2, auto_v6_tunnel);
            SetDsPhyPortExt2(V, autoIpv6TunnelForHash0_f, &ds2, auto_v6_tunnel_hash0);
            SetDsPhyPortExt2(V, ipv4VxlanTunnelHashEn0_f, &ds2, v4_vxlan_en);
            SetDsPhyPortExt2(V, ipv6NvgreTunnelHashEn0_f, &ds2, v6_nvgre_en);
            SetDsPhyPortExt2(V, ipv6VxlanTunnelHashEn0_f, &ds2, v6_vxlan_en);
            SetDsPhyPortExt2(V, mcMacDisableHash0_f , &ds2, (p_prop->hash_mcast_dis ? 1 : 0));
            SetDsPhyPortExt2(V, hash0VlanRangeEn_f, &ds2, (p_prop->hash_vlan_range_dis? 0: 1));
            SetDsPhyPortExt2(V, hash0VlanRange1En_f, &ds2, (p_prop->hash_vlan_range_dis? 0: 1));
            SetDsPhyPortExt2(V, hash0XKeyEn_f, &ds2, (p_prop->flex_key_en? 1: 0));
            if (p_prop->hash_field_sel_id_valid)
            {
                SetDsPhyPortExt2(V, sclFlowHashFieldSel_f, &ds2, p_prop->hash_field_sel_id);
            }
        }
        else if (1 == p_prop->scl_id)
        {
            if ((CTC_PORT_IGS_SCL_HASH_TYPE_L2 == p_prop->hash_type) && !DRV_FROM_TMM(lchip))
            {
                return CTC_E_INVALID_PARAM;
            }

            SetDsPhyPortExt(V, userIdPortHash2Type_f, &ds, scl_type_para.drv_hash_type);
            SetDsPhyPortExt(V, hash2UseDa_f, &ds, scl_type_para.use_macda);
            SetDsPhyPortExt(V, userIdTcam2En_f, &ds,  scl_type_para.tcam_en);
            SetDsPhyPortExt(V, userIdTcam2Type_f, &ds,  scl_type_para.drv_tcam_type);
            SetDsPhyPortExt(V, hashLookup2UseLabel_f , &ds, (p_prop->class_id_en ? 1 : 0));
            SetDsPhyPortExt(V, userIdLabel2_f, &ds, p_prop->class_id);
            SetDsPhyPortExt(V, userId2UseLogicPort_f , &ds, (p_prop->use_logic_port_en ? 1 : 0));
            SetDsPhyPortExt(V, tcamUseLogicPort_f , &ds, (p_prop->use_logic_port_en ? 1 : 0));

            SetDsPhyPortExt(V, ipv4TunnelHashEn2_f, &ds, ipv4_tunnel_en);
            SetDsPhyPortExt(V, ipv6TunnelHashEn1_f, &ds, v6_tunnel_en);
            SetDsPhyPortExt(V, ipv4GreTunnelHashEn2_f, &ds, ipv4_gre_tunnel_en);
            SetDsPhyPortExt(V, autoTunnelEn_f, &ds, auto_tunnel);
            SetDsPhyPortExt(V, tunnelRpfCheck_f, &ds, rpf_check_en);
            SetDsPhyPortExt(V, autoTunnelForHash1_f, &ds, auto_tunnel_hash1);
            SetDsPhyPortExt(V, autoIpv6TunnelEn_f, &ds, auto_v6_tunnel);
            SetDsPhyPortExt(V, autoIpv6TunnelForHash0_f, &ds, auto_v6_tunnel_hash0);
            SetDsPhyPortExt(V, ipv4VxlanTunnelHashEn2_f, &ds, v4_vxlan_en);
            SetDsPhyPortExt(V, ipv6NvgreTunnelHashEn2_f, &ds, v6_nvgre_en);
            SetDsPhyPortExt(V, ipv6VxlanTunnelHashEn2_f, &ds, v6_vxlan_en);
            /**< [TM] Append hash and tcam vlan range enable */
            SetDsPhyPortExt(V, hash2VlanRangeEn_f, &ds, !(p_prop->hash_vlan_range_dis));
            SetDsPhyPortExt(V, tcam2VlanRangeEn_f, &ds, !(p_prop->tcam_vlan_range_dis));
            /**< [TM] Append tcam use logic port */
            SetDsPhyPortExt(V, tcam2UseLogicPort_f , &ds, (p_prop->use_logic_port_en ? 1 : 0));
            /**< [TM] Append hash mcast disable */
            SetDsPhyPortExt(V, mcMacDisableHash1_f , &ds, (p_prop->hash_mcast_dis ? 1 : 0));
            SetDsPhyPortExt(V, defaultEntry1Ignore_f, &ds, field_value);
            
            SetDsPhyPortExt2(V, userIdPortHash1Type_f, &ds2, scl_type_para.drv_hash_type);
            SetDsPhyPortExt2(V, hash1UseDa_f, &ds2, scl_type_para.use_macda);
            SetDsPhyPortExt2(V, hashLookup1UseLabel_f , &ds2, (p_prop->class_id_en ? 1 : 0));
            SetDsPhyPortExt2(V, userIdLabel1_f, &ds2, p_prop->class_id);
            SetDsPhyPortExt2(V, userId1UseLogicPort_f , &ds2, (p_prop->use_logic_port_en ? 1 : 0));
            SetDsPhyPortExt2(V, ipv4TunnelHashEn1_f, &ds2, ipv4_tunnel_en);
            SetDsPhyPortExt2(V, ipv6TunnelHashEn1_f, &ds2, v6_tunnel_en);
            SetDsPhyPortExt2(V, ipv4GreTunnelHashEn1_f, &ds2, ipv4_gre_tunnel_en);
            SetDsPhyPortExt2(V, autoTunnelEn_f, &ds2, auto_tunnel);
            SetDsPhyPortExt2(V, tunnelRpfCheck_f, &ds2, rpf_check_en);
            SetDsPhyPortExt2(V, autoTunnelForHash0_f, &ds2, auto_tunnel_hash1);
            SetDsPhyPortExt2(V, autoIpv6TunnelEn_f, &ds2, auto_v6_tunnel);
            SetDsPhyPortExt2(V, autoIpv6TunnelForHash0_f, &ds2, auto_v6_tunnel_hash0);
            SetDsPhyPortExt2(V, ipv4VxlanTunnelHashEn1_f, &ds2, v4_vxlan_en);
            SetDsPhyPortExt2(V, ipv6NvgreTunnelHashEn1_f, &ds2, v6_nvgre_en);
            SetDsPhyPortExt2(V, ipv6VxlanTunnelHashEn1_f, &ds2, v6_vxlan_en);
            SetDsPhyPortExt2(V, mcMacDisableHash1_f , &ds2, (p_prop->hash_mcast_dis ? 1 : 0));
            SetDsPhyPortExt2(V, hash1VlanRangeEn_f, &ds2, (p_prop->hash_vlan_range_dis? 0: 1));
            SetDsPhyPortExt2(V, hash1VlanRange1En_f, &ds2, (p_prop->hash_vlan_range_dis? 0: 1));
            SetDsPhyPortExt2(V, hash1XKeyEn_f, &ds2, (p_prop->flex_key_en? 1: 0));
            if (p_prop->hash_field_sel_id_valid)
            {
                SetDsPhyPortExt2(V, sclFlowHash1FieldSel_f, &ds2, p_prop->hash_field_sel_id);
            }
        }
        else if (2 == p_prop->scl_id)       /**< [TM] */
        {
            /**< [TM] Refer to scl 0/1 */
            SetDsPhyPortExt(V, userIdTcam3En_f, &ds, scl_type_para.tcam_en);
            SetDsPhyPortExt(V, userIdTcam3Type_f, &ds, scl_type_para.drv_tcam_type);
            SetDsPhyPortExt(V, userIdLabel3_f, &ds, p_prop->class_id);
            /**< [TM] Append tcam vlan range enable */
            SetDsPhyPortExt(V, tcam3VlanRangeEn_f, &ds, !(p_prop->tcam_vlan_range_dis));
            /**< [TM] Append tcam use logic port */
            SetDsPhyPortExt(V, tcam3UseLogicPort_f , &ds, (p_prop->use_logic_port_en ? 1 : 0));

            SetDsPhyPortExt2(V, userIdTcam0En_f, &ds2, scl_type_para.tcam_en);
            SetDsPhyPortExt2(V, userIdTcam0Type_f, &ds2, scl_type_para.drv_tcam_type);
            SetDsPhyPortExt2(V, tcam0VlanRangeEn_f, &ds2, (p_prop->tcam_vlan_range_dis? 0: 1));
            SetDsPhyPortExt2(V, tcam0VlanRange1En_f, &ds2, (p_prop->tcam_vlan_range_dis? 0: 1));
            SetDsPhyPortExt2(V, tcam0UseLogicPort_f , &ds2, (p_prop->use_logic_port_en ? 1 : 0));
            SetDsPhyPortExt2(V, tcamLabel0_f, &ds2, p_prop->class_id);
            SetDsPhyPortExt2(V, tcam0XKeyEn_f, &ds2, (p_prop->flex_key_en? 1: 0));
        }
        else if (3 == p_prop->scl_id)       /**< [TM] */
        {
            /**< [TM] Refer to scl 0/1 */
            SetDsPhyPortExt(V, userIdTcam4En_f, &ds, scl_type_para.tcam_en);
            SetDsPhyPortExt(V, userIdTcam4Type_f, &ds, scl_type_para.drv_tcam_type);
            SetDsPhyPortExt(V, userIdLabel4_f, &ds, p_prop->class_id);
            /**< [TM] Append tcam vlan range enable */
            SetDsPhyPortExt(V, tcam4VlanRangeEn_f, &ds, !(p_prop->tcam_vlan_range_dis));
            /**< [TM] Append tcam use logic port */
            SetDsPhyPortExt(V, tcam4UseLogicPort_f , &ds, (p_prop->use_logic_port_en ? 1 : 0));

            SetDsPhyPortExt2(V, userIdTcam1En_f, &ds2, scl_type_para.tcam_en);
            SetDsPhyPortExt2(V, userIdTcam1Type_f, &ds2, scl_type_para.drv_tcam_type);
            SetDsPhyPortExt2(V, tcam1VlanRangeEn_f, &ds2, !(p_prop->tcam_vlan_range_dis));
            SetDsPhyPortExt2(V, tcam1VlanRange1En_f, &ds2, !(p_prop->tcam_vlan_range_dis));
            SetDsPhyPortExt2(V, tcam1UseLogicPort_f , &ds2, (p_prop->use_logic_port_en ? 1 : 0));
            SetDsPhyPortExt2(V, tcamLabel1_f, &ds2, p_prop->class_id);
            SetDsPhyPortExt2(V, tcam1XKeyEn_f, &ds2, (p_prop->flex_key_en? 1: 0));
        }
        else
        {
            ;
        }

        switch (p_prop->action_type)
        {
            case CTC_PORT_SCL_ACTION_TYPE_SCL:
                if (0 == p_prop->scl_id)
                {
                    SetDsPhyPortExt(V, tcam1IsUserId_f, &ds, 1);
                    SetDsPhyPortExt(V, tcam1IsSclFlow_f, &ds, 0);
                    SetDsPhyPortExt(V, sclFlowHashEn_f, &ds, 0);
                }
                else if (1 == p_prop->scl_id)
                {
                    SetDsPhyPortExt(V, tcam2IsUserId_f, &ds, 1);
                    SetDsPhyPortExt(V, tcam2IsSclFlow_f, &ds, 0);
                    /**< [TM] */
                    SetDsPhyPortExt(V, sclFlowHash2En_f, &ds, 0);
                }
                else
                {
                    ;
                }
                break;
            case CTC_PORT_SCL_ACTION_TYPE_FLOW:
                if (0 == p_prop->scl_id)
                {
                    SetDsPhyPortExt(V, tcam1IsUserId_f, &ds, 0);
                    SetDsPhyPortExt(V, tcam1IsSclFlow_f, &ds, 1);
                    SetDsPhyPortExt(V, sclFlowHashEn_f, &ds, 1);
                }
                else if (1 == p_prop->scl_id)
                {
                    if ((p_prop->hash_type != CTC_PORT_IGS_SCL_HASH_TYPE_DISABLE) && !DRV_FROM_TMM(lchip))
                    {
                        return CTC_E_INVALID_PARAM;
                    }
                    SetDsPhyPortExt(V, tcam2IsUserId_f, &ds, 0);
                    SetDsPhyPortExt(V, tcam2IsSclFlow_f, &ds, 1);
                    /**< [TM] */
                    SetDsPhyPortExt(V, sclFlowHash2En_f, &ds, 1);
                }
                else
                {
                    ;
                }
                break;
            case CTC_PORT_SCL_ACTION_TYPE_TUNNEL:
                if (0 == p_prop->scl_id)
                {
                    SetDsPhyPortExt(V, tcam1IsUserId_f, &ds, 0);
                    SetDsPhyPortExt(V, tcam1IsSclFlow_f, &ds, 0);
                    SetDsPhyPortExt(V, sclFlowHashEn_f, &ds, 0);
                }
                else if (1 == p_prop->scl_id)
                {
                    SetDsPhyPortExt(V, tcam2IsUserId_f, &ds, 0);
                    SetDsPhyPortExt(V, tcam2IsSclFlow_f, &ds, 0);
                    /**< [TM] */
                    SetDsPhyPortExt(V, sclFlowHash2En_f, &ds, 0);
                }
                else
                {
                    ;
                }
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }

        vlan_high_priority = scl_type_para.vlan_high_priority;
        cmd = DRV_IOW(DsPhyPortExt_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));
        cmd = DRV_IOW(DsPhyPortExt2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds2));
        cmd = DRV_IOW(DsSrcPort_t, DsSrcPort_ingressTagHighPriority_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &vlan_high_priority));

    }
    else if (CTC_EGRESS == p_prop->direction)
    {
        DsDestPort_m ds;

        cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));

        if (0 == p_prop->scl_id)
        {
            SetDsDestPort(V, vlanHash1Type_f, &ds, scl_type_para.drv_hash_type);
            SetDsDestPort(V, vlanHash1UseLogicPort_f, &ds, p_prop->use_logic_port_en);
            SetDsDestPort(V, vlanHash1UseLabel_f, &ds, p_prop->class_id_en);
            SetDsDestPort(V, vlanHash1XKeyEn_f, &ds, (p_prop->hash_type == CTC_PORT_EGS_SCL_HASH_TYPE_NSH ||p_prop->flex_key_en)?1:0);
        }
        else if (1 == p_prop->scl_id)
        {
            SetDsDestPort(V, vlanHash2Type_f, &ds, scl_type_para.drv_hash_type);
            SetDsDestPort(V, vlanHash2UseLogicPort_f, &ds, p_prop->use_logic_port_en);
            SetDsDestPort(V, vlanHash2UseLabel_f, &ds, p_prop->class_id_en);
            SetDsDestPort(V, vlanHash1DefaultEntryValid_f, &ds, (scl_type_para.drv_hash_type?0:1));
            SetDsDestPort(V, vlanHash2XKeyEn_f, &ds, (p_prop->hash_type == CTC_PORT_EGS_SCL_HASH_TYPE_NSH ||p_prop->flex_key_en)?1:0);
        }

        SetDsDestPort(V, vlanHashLabel_f, &ds, p_prop->class_id);
        SetDsDestPort(V, vlanHashUseLogicPort_f, &ds, p_prop->use_logic_port_en);
        SetDsDestPort(V, vlanHashUseLabel_f, &ds, p_prop->class_id_en);

        cmd = DRV_IOW(DsDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));
    }
    return CTC_E_NONE;
}

int32
sys_usw_port_get_scl_property(uint8 lchip, uint32 gport, ctc_port_scl_property_t* p_prop)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    uint8 tcam_is_userid = 0;
    uint8 tcam_is_scl_flow = 0;
    sys_scl_type_para_t scl_type_para;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    CTC_PTR_VALID_CHECK(p_prop);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    CTC_MAX_VALUE_CHECK(p_prop->direction, CTC_BOTH_DIRECTION - 1);
    CTC_MAX_VALUE_CHECK(p_prop->scl_id, (MCHIP_CAP(SYS_CAP_SCL_IGS_TCAM_NUM)-1));

    if (1 < p_prop->scl_id && CTC_EGRESS == p_prop->direction)
    {
        return CTC_E_NOT_SUPPORT;
    }

    sal_memset(&scl_type_para, 0, sizeof(sys_scl_type_para_t));

    if (CTC_INGRESS == p_prop->direction)
    {
        DsPhyPortExt_m ds;
        DsPhyPortExt2_m ds2;
        uint16         ignore_bmp = 0xFF;

        cmd = DRV_IOR(DsPhyPortExt_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));

        cmd = DRV_IOR(DsPhyPortExt2_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds2));

        if (0 == p_prop->scl_id)
        {
            scl_type_para.drv_hash_type = GetDsPhyPortExt(V, userIdPortHash1Type_f, &ds);
            scl_type_para.use_macda = GetDsPhyPortExt(V, hash1UseDa_f, &ds);
            scl_type_para.tcam_en = GetDsPhyPortExt(V, userIdTcam1En_f, &ds);
            scl_type_para.drv_tcam_type = GetDsPhyPortExt(V, userIdTcam1Type_f, &ds);
            scl_type_para.tunnel_en = GetDsPhyPortExt(V, ipv4TunnelHashEn1_f, &ds) && GetDsPhyPortExt(V, ipv4GreTunnelHashEn1_f, &ds);
            scl_type_para.auto_tunnel = GetDsPhyPortExt(V, autoTunnelEn_f, &ds);
            scl_type_para.auto_tunnel &= GetDsPhyPortExt(V, autoTunnelForHash1_f, &ds);
            /* nvgre full condition */
            scl_type_para.nvgre_en = (GetDsPhyPortExt(V, ipv4GreTunnelHashEn1_f, &ds) || GetDsPhyPortExt(V, ipv6NvgreTunnelHashEn1_f, &ds)) && !scl_type_para.tunnel_en;
            /* vxlan full condition */
            scl_type_para.vxlan_en = GetDsPhyPortExt(V, ipv4VxlanTunnelHashEn1_f, &ds) || GetDsPhyPortExt(V, ipv6VxlanTunnelHashEn1_f, &ds);
            p_prop->class_id_en = GetDsPhyPortExt(V, hashLookup1UseLabel_f , &ds);
            p_prop->class_id = GetDsPhyPortExt(V, userIdLabel1_f , &ds);
            p_prop->use_logic_port_en = GetDsPhyPortExt(V, userId1UseLogicPort_f , &ds);
            tcam_is_userid = GetDsPhyPortExt(V, tcam1IsUserId_f, &ds);
            tcam_is_scl_flow = GetDsPhyPortExt(V, tcam1IsSclFlow_f, &ds);
            p_prop->hash_vlan_range_dis = !GetDsPhyPortExt(V, hash1VlanRangeEn_f, &ds);
            p_prop->tcam_vlan_range_dis = !GetDsPhyPortExt(V, tcam1VlanRangeEn_f, &ds);
            if(DRV_FROM_TMM(lchip))
            {
                scl_type_para.drv_hash_type = GetDsPhyPortExt2(V, userIdPortHash0Type_f, &ds2);
                scl_type_para.use_macda = GetDsPhyPortExt2(V, hash0UseDa_f, &ds2);
                scl_type_para.tunnel_en = GetDsPhyPortExt2(V, ipv4TunnelHashEn0_f, &ds2) && GetDsPhyPortExt2(V, ipv4GreTunnelHashEn0_f, &ds2);
                scl_type_para.auto_tunnel = GetDsPhyPortExt2(V, autoTunnelEn_f, &ds2);
                scl_type_para.auto_tunnel &= GetDsPhyPortExt2(V, autoTunnelForHash0_f, &ds2);
                /* nvgre full condition */
                scl_type_para.nvgre_en = (GetDsPhyPortExt2(V, ipv4GreTunnelHashEn0_f, &ds2) || GetDsPhyPortExt2(V, ipv6NvgreTunnelHashEn0_f, &ds2)) && !scl_type_para.tunnel_en;
                /* vxlan full condition */
                scl_type_para.vxlan_en = GetDsPhyPortExt2(V, ipv4VxlanTunnelHashEn0_f, &ds2) || GetDsPhyPortExt2(V, ipv6VxlanTunnelHashEn0_f, &ds2);
                p_prop->class_id_en = GetDsPhyPortExt2(V, hashLookup0UseLabel_f , &ds2);
                p_prop->class_id = GetDsPhyPortExt2(V, userIdLabel0_f , &ds2);
                p_prop->use_logic_port_en = GetDsPhyPortExt2(V, userId0UseLogicPort_f , &ds2);
                p_prop->hash_vlan_range_dis = !GetDsPhyPortExt2(V, hash0VlanRangeEn_f, &ds2);
                p_prop->tcam_vlan_range_dis = 1;
                p_prop->hash_field_sel_id = GetDsPhyPortExt2(V, sclFlowHashFieldSel_f, &ds2);
                p_prop->flex_key_en = GetDsPhyPortExt2(V, hash0XKeyEn_f, &ds2);
            }
            ignore_bmp = GetDsPhyPortExt(V, defaultEntry0Ignore_f, &ds);
        }
        else if (1 == p_prop->scl_id)
        {
            if ((CTC_PORT_IGS_SCL_HASH_TYPE_L2 == p_prop->hash_type) && !DRV_FROM_TMM(lchip))
            {
                return CTC_E_INVALID_PARAM;
            }

            scl_type_para.drv_hash_type = GetDsPhyPortExt(V, userIdPortHash2Type_f, &ds);
            scl_type_para.use_macda = GetDsPhyPortExt(V, hash2UseDa_f, &ds);
            scl_type_para.tcam_en = GetDsPhyPortExt(V, userIdTcam2En_f, &ds);
            scl_type_para.drv_tcam_type = GetDsPhyPortExt(V, userIdTcam2Type_f, &ds);
            scl_type_para.tunnel_en = GetDsPhyPortExt(V, ipv4TunnelHashEn2_f, &ds) && GetDsPhyPortExt(V, ipv4GreTunnelHashEn2_f, &ds);
            scl_type_para.tunnel_rpf_check = scl_type_para.tunnel_en && GetDsPhyPortExt(V, tunnelRpfCheck_f, &ds);
            scl_type_para.auto_tunnel = GetDsPhyPortExt(V, autoTunnelEn_f, &ds);
            scl_type_para.auto_tunnel &= (!GetDsPhyPortExt(V, autoTunnelForHash1_f, &ds));
            /* nvgre full condition */
            scl_type_para.nvgre_en = (GetDsPhyPortExt(V, ipv4GreTunnelHashEn2_f, &ds) || GetDsPhyPortExt(V, ipv6NvgreTunnelHashEn2_f, &ds)) && !scl_type_para.tunnel_en;
            /* vxlan full condition */
            scl_type_para.vxlan_en = GetDsPhyPortExt(V, ipv4VxlanTunnelHashEn2_f, &ds) || GetDsPhyPortExt(V, ipv6VxlanTunnelHashEn2_f, &ds);
            p_prop->class_id_en = GetDsPhyPortExt(V, hashLookup2UseLabel_f , &ds);
            p_prop->class_id = GetDsPhyPortExt(V, userIdLabel2_f , &ds);
            p_prop->use_logic_port_en = GetDsPhyPortExt(V, userId2UseLogicPort_f , &ds);
            tcam_is_userid = GetDsPhyPortExt(V, tcam2IsUserId_f, &ds);
            tcam_is_scl_flow = GetDsPhyPortExt(V, tcam2IsSclFlow_f, &ds);
            p_prop->hash_vlan_range_dis = !GetDsPhyPortExt(V, hash2VlanRangeEn_f, &ds);
            p_prop->tcam_vlan_range_dis = !GetDsPhyPortExt(V, tcam2VlanRangeEn_f, &ds);
            if(DRV_FROM_TMM(lchip))
            {
                scl_type_para.drv_hash_type = GetDsPhyPortExt2(V, userIdPortHash1Type_f, &ds2);
                scl_type_para.use_macda = GetDsPhyPortExt2(V, hash1UseDa_f, &ds2);
                scl_type_para.tunnel_en = GetDsPhyPortExt2(V, ipv4TunnelHashEn1_f, &ds2) && GetDsPhyPortExt2(V, ipv4GreTunnelHashEn1_f, &ds2);
                scl_type_para.tunnel_rpf_check = scl_type_para.tunnel_en && GetDsPhyPortExt2(V, tunnelRpfCheck_f, &ds2);
                scl_type_para.auto_tunnel = GetDsPhyPortExt2(V, autoTunnelEn_f, &ds2);
                scl_type_para.auto_tunnel &= (!GetDsPhyPortExt2(V, autoTunnelForHash0_f, &ds2));
                /* nvgre full condition */
                scl_type_para.nvgre_en = (GetDsPhyPortExt2(V, ipv4GreTunnelHashEn1_f, &ds2) || GetDsPhyPortExt2(V, ipv6NvgreTunnelHashEn1_f, &ds2)) && !scl_type_para.tunnel_en;
                /* vxlan full condition */
                scl_type_para.vxlan_en = GetDsPhyPortExt2(V, ipv4VxlanTunnelHashEn1_f, &ds2) || GetDsPhyPortExt2(V, ipv6VxlanTunnelHashEn1_f, &ds2);
                p_prop->class_id_en = GetDsPhyPortExt2(V, hashLookup1UseLabel_f , &ds2);
                p_prop->class_id = GetDsPhyPortExt2(V, userIdLabel1_f , &ds2);
                p_prop->use_logic_port_en = GetDsPhyPortExt2(V, userId1UseLogicPort_f , &ds2);
                p_prop->hash_vlan_range_dis = !GetDsPhyPortExt2(V, hash1VlanRangeEn_f, &ds2);
                p_prop->tcam_vlan_range_dis = 1;
                p_prop->hash_field_sel_id = GetDsPhyPortExt2(V, sclFlowHash1FieldSel_f, &ds2);
                p_prop->flex_key_en = GetDsPhyPortExt2(V, hash1XKeyEn_f, &ds2);
            }
            ignore_bmp = GetDsPhyPortExt(V, defaultEntry1Ignore_f, &ds);
        }
        else if (2 == p_prop->scl_id)
        {
            /**< [TM] Refer to scl 0/1 */
            scl_type_para.tcam_en = GetDsPhyPortExt(V, userIdTcam3En_f, &ds);
            scl_type_para.drv_tcam_type = GetDsPhyPortExt(V, userIdTcam3Type_f, &ds);
            p_prop->class_id = GetDsPhyPortExt(V, userIdLabel3_f, &ds);
            /**< [TM] Append tcam vlan range enable */
            p_prop->tcam_vlan_range_dis = !GetDsPhyPortExt(V, tcam3VlanRangeEn_f, &ds);
            /**< [TM] Append tcam use logic port */
            p_prop->use_logic_port_en = GetDsPhyPortExt(V, tcam3UseLogicPort_f , &ds);
            if (DRV_FROM_TMM(lchip))
            {
                scl_type_para.tcam_en = GetDsPhyPortExt2(V, userIdTcam0En_f, &ds2);
                scl_type_para.drv_tcam_type = GetDsPhyPortExt2(V, userIdTcam0Type_f, &ds2);
                p_prop->tcam_vlan_range_dis = !GetDsPhyPortExt2(V, tcam0VlanRangeEn_f, &ds2);
                p_prop->hash_vlan_range_dis = 1;
                p_prop->class_id = GetDsPhyPortExt2(V, tcamLabel0_f, &ds2);
                p_prop->use_logic_port_en = GetDsPhyPortExt2(V, tcam0UseLogicPort_f , &ds2);
                p_prop->flex_key_en = GetDsPhyPortExt2(V, tcam0XKeyEn_f, &ds2);
            }
        }
        else if (3 == p_prop->scl_id)
        {
            /**< [TM] Refer to scl 0/1 */
            scl_type_para.tcam_en = GetDsPhyPortExt(V, userIdTcam4En_f, &ds);
            scl_type_para.drv_tcam_type = GetDsPhyPortExt(V, userIdTcam4Type_f, &ds);
            p_prop->class_id = GetDsPhyPortExt(V, userIdLabel4_f, &ds);
            /**< [TM] Append tcam vlan range enable */
            p_prop->tcam_vlan_range_dis = !GetDsPhyPortExt(V, tcam4VlanRangeEn_f, &ds);
            /**< [TM] Append tcam use logic port */
            p_prop->use_logic_port_en = GetDsPhyPortExt(V, tcam4UseLogicPort_f , &ds);
            if (DRV_FROM_TMM(lchip))
            {
                scl_type_para.tcam_en = GetDsPhyPortExt2(V, userIdTcam1En_f, &ds2);
                scl_type_para.drv_tcam_type = GetDsPhyPortExt2(V, userIdTcam1Type_f, &ds2);
                p_prop->tcam_vlan_range_dis = !GetDsPhyPortExt2(V, tcam1VlanRangeEn_f, &ds2) ;
                p_prop->hash_vlan_range_dis = 1;
                p_prop->class_id = GetDsPhyPortExt2(V, tcamLabel1_f, &ds2);
                p_prop->use_logic_port_en = GetDsPhyPortExt2(V, tcam1UseLogicPort_f , &ds2);
                p_prop->flex_key_en = GetDsPhyPortExt2(V, tcam1XKeyEn_f, &ds2);
            }
        }
        else
        {
            ;
        }

        /*get default entry merge bitmap, for example, 
            1. defaultEntry0Ignore is 0b'1100 --> merge bmp 0b'0011
            2. defaultEntry0Ignore is 0b'1110 --> merge bmp 0b'0000 (also is 0b'0001)*/
        if(p_prop->scl_id < 2)
        {
            ignore_bmp = ((1<<MCHIP_CAP(SYS_CAP_SCL_IGS_TCAM_NUM))-1) & (~ignore_bmp);
            p_prop->default_merge_bmp = (ignore_bmp & (~(1<<p_prop->scl_id))) ?  ignore_bmp : 0;
        }
        if (tcam_is_scl_flow)
        {
            p_prop->action_type = CTC_PORT_SCL_ACTION_TYPE_FLOW;
        }
        else if (tcam_is_userid)
        {
            p_prop->action_type = CTC_PORT_SCL_ACTION_TYPE_SCL;
        }
        else
        {
            p_prop->action_type = CTC_PORT_SCL_ACTION_TYPE_TUNNEL;
        }
    }
    else if (CTC_EGRESS == p_prop->direction)
    {
        DsDestPort_m ds;

        cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds));

        if (0 == p_prop->scl_id)
        {
            scl_type_para.drv_hash_type = GetDsDestPort(V, vlanHash1Type_f, &ds);
            p_prop->use_logic_port_en = GetDsDestPort(V, vlanHash1UseLogicPort_f, &ds);
            p_prop->class_id_en = GetDsDestPort(V, vlanHash1UseLabel_f, &ds);
            if (scl_type_para.drv_hash_type != 0xF)
            {
                p_prop->flex_key_en = GetDsDestPort(V, vlanHash1XKeyEn_f, &ds);
            }
        }
        else
        {
            scl_type_para.drv_hash_type = GetDsDestPort(V, vlanHash2Type_f, &ds);
            p_prop->use_logic_port_en = GetDsDestPort(V, vlanHash2UseLogicPort_f, &ds);
            p_prop->class_id_en = GetDsDestPort(V, vlanHash2UseLabel_f, &ds);
            if (scl_type_para.drv_hash_type != 0xF)
            {
                p_prop->flex_key_en = GetDsDestPort(V, vlanHash2XKeyEn_f, &ds);
            }

        }

        p_prop->class_id = GetDsDestPort(V, vlanHashLabel_f, &ds);
        if (DRV_FLD_IS_EXISIT(DsDestPort_t, DsDestPort_vlanHashUseLabel_f))
        {
            p_prop->class_id_en = GetDsDestPort(V, vlanHashUseLabel_f, &ds);
        }
        if (DRV_FLD_IS_EXISIT(DsDestPort_t, DsDestPort_vlanHashUseLogicPort_f))
        {
            p_prop->use_logic_port_en = GetDsDestPort(V, vlanHashUseLogicPort_f, &ds);
        }
    }

    CTC_ERROR_RETURN(_sys_usw_port_unmap_scl_type(lchip, p_prop->direction, &scl_type_para));

    p_prop->hash_type = scl_type_para.ctc_hash_type;
    p_prop->tcam_type = scl_type_para.ctc_tcam_type;
    if (DRV_FROM_TMM(lchip) && ((0 == p_prop->scl_id) || (1 == p_prop->scl_id)) && (CTC_PORT_IGS_SCL_HASH_TYPE_DISABLE != scl_type_para.ctc_hash_type))
    {
        p_prop->tcam_type = CTC_PORT_IGS_SCL_TCAM_TYPE_RESOLVE_CONFLICT;
    }
    return CTC_E_NONE;
}

static INLINE int32
_sys_at_port_set_acl_property(uint8 lchip, uint16 lport, ctc_acl_property_t* p_prop, uint8 sys_lkup_type, uint8 gport_type)
{
    DsSrcPortAclCtl_m ds_src_port;
    DsDestPortAclCtl_m ds_dest_port;
    uint32 cmd = 0;
    uint8  step = 0;

    if (p_prop->direction == CTC_INGRESS)
    {
        step = DsSrcPortAclCtl_gAcl_1_aclLabel_f - DsSrcPortAclCtl_gAcl_0_aclLabel_f;
        cmd = DRV_IOR(DsSrcPortAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));
        SetDsSrcPortAclCtl(V, gAcl_0_aclLabel_f + p_prop->acl_priority * step, &ds_src_port, p_prop->acl_en? p_prop->class_id: 0);
        SetDsSrcPortAclCtl(V, gAcl_0_aclLookupType_f + p_prop->acl_priority * step, &ds_src_port, p_prop->acl_en? sys_lkup_type: 0);
        SetDsSrcPortAclCtl(V, gAcl_0_aclUseGlobalPortType_f + p_prop->acl_priority * step, &ds_src_port, p_prop->acl_en? gport_type: 0);
        SetDsSrcPortAclCtl(V, gAcl_0_aclUsePIVlan_f + p_prop->acl_priority * step, &ds_src_port, p_prop->acl_en? !!CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN): 0);
        cmd = DRV_IOW(DsSrcPortAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));
    }
    else
    {
        step = DsDestPortAclCtl_gAcl_1_aclLabel_f - DsDestPortAclCtl_gAcl_0_aclLabel_f;
        cmd = DRV_IOR(DsDestPortAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_dest_port));
        SetDsDestPortAclCtl(V, gAcl_0_aclLabel_f + p_prop->acl_priority * step, &ds_dest_port, p_prop->acl_en? p_prop->class_id: 0);
        SetDsDestPortAclCtl(V, gAcl_0_aclLookupType_f + p_prop->acl_priority * step, &ds_dest_port, p_prop->acl_en? sys_lkup_type: 0);
        SetDsDestPortAclCtl(V, gAcl_0_aclUseGlobalPortType_f + p_prop->acl_priority * step, &ds_dest_port, p_prop->acl_en? gport_type: 0);
        SetDsDestPortAclCtl(V, gAcl_0_aclUsePIVlan_f + p_prop->acl_priority * step, &ds_dest_port, p_prop->acl_en? !!CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN): 0);
        cmd = DRV_IOW(DsDestPortAclCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_dest_port));
    }
    return CTC_E_NONE;
}

int32
_sys_usw_port_set_acl_property(uint8 lchip, uint16 lport, ctc_acl_property_t* p_prop)
{
    uint8  acl_priority = 0;
    uint32 cmd = 0;
    uint32 step = 0;
    uint8  sys_lkup_type = 0;
    uint8  gport_type = 0;

    DsSrcPort_m ds_src_port;
    DsDestPort_m ds_dest_port;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "lport:%d, acl pri:%d\n", lport, p_prop->acl_priority);

    if(DRV_IS_TMM(lchip) && p_prop->acl_en && p_prop->direction != CTC_INGRESS && 
        (p_prop->tcam_lkup_type >= CTC_ACL_TCAM_LKUP_TYPE_CID))
    {
        return CTC_E_NOT_SUPPORT;
    }

    if (CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_HASH_LKUP))
    {
        if(SYS_FTM_SPEC(lchip, CTC_FTM_SPEC_ACL_FLOW) == 0)
        {
            return CTC_E_NO_RESOURCE;
        }
        cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));
        if(p_prop->acl_en)
        {
            SetDsSrcPort(V, aclFlowHashFieldSel_f, &ds_src_port, p_prop->hash_field_sel_id);
            SetDsSrcPort(V, aclFlowHashType_f,     &ds_src_port, p_prop->hash_lkup_type);
            SetDsSrcPort(V, aclFlowHashExtDataEn_f, &ds_src_port, (p_prop->hash_lkup_type==CTC_ACL_HASH_LKUP_TYPE_NSH)? 1: 0);
            SetDsSrcPort(V, flowHashUsePiVlan_f,     &ds_src_port, CTC_FLAG_ISSET(p_prop->flag,CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN)?1:0);
            SetDsSrcPort(V, aclFlowHashXKeyEn_f,     &ds_src_port, p_prop->flex_key_en);
        }
        else
        {
            SetDsSrcPort(V, aclFlowHashFieldSel_f, &ds_src_port, 0);
            SetDsSrcPort(V, aclFlowHashType_f,     &ds_src_port, 0);
            SetDsSrcPort(V, aclFlowHashExtDataEn_f, &ds_src_port, 0);
            SetDsSrcPort(V, flowHashUsePiVlan_f,   &ds_src_port, 0);
            SetDsSrcPort(V, aclFlowHashXKeyEn_f,   &ds_src_port, 0);
        }
        cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip,lport,cmd,&ds_src_port));

        return CTC_E_NONE;
    }
    acl_priority = p_prop->acl_priority;
    sys_lkup_type = sys_usw_map_acl_tcam_lkup_type(lchip, p_prop->tcam_lkup_type);
    if(CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_PORT_BITMAP))
    {
        gport_type = DRV_ENUM(DRV_FLOWPORTTYPE_BITMAP);
    }
    else if(CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_METADATA))
    {
        gport_type = DRV_ENUM(DRV_FLOWPORTTYPE_METADATA);
    }
    else if(CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_LOGIC_PORT))
    {
        gport_type = DRV_ENUM(DRV_FLOWPORTTYPE_LPORT);
    }
    else
    {
        gport_type = DRV_ENUM(DRV_FLOWPORTTYPE_GPORT);
    }

    if (DRV_FROM_AT(lchip))
    {
        CTC_ERROR_RETURN(_sys_at_port_set_acl_property(lchip, lport, p_prop, sys_lkup_type, gport_type));
        return CTC_E_NONE;
    }
    if(p_prop->direction == CTC_INGRESS )
    {
        cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));
        DRV_SET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclLabel", &ds_src_port, p_prop->acl_en? p_prop->class_id: 0, "_0_", p_prop->acl_priority);
        DRV_SET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclUseGlobalPortType", &ds_src_port, p_prop->acl_en? gport_type: 0, "_0_", p_prop->acl_priority);
        DRV_SET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclUsePIVlan", &ds_src_port, p_prop->acl_en? !!CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN): 0, "_0_", p_prop->acl_priority);
        DRV_SET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclLookupType", &ds_src_port, p_prop->acl_en? sys_lkup_type: 0, "_0_", p_prop->acl_priority);
        DRV_SET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclUseCapwapInfo", &ds_src_port, p_prop->acl_en? !!CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_WLAN): 0, "_0_", p_prop->acl_priority);

        /*write hw*/
        cmd = DRV_IOW(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip,lport,cmd,&ds_src_port));
    }
    else
    {
        step = DsDestPort_gAcl_1_aclLookupType_f - DsDestPort_gAcl_0_aclLookupType_f;
        cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_dest_port));

        if(0 == p_prop->acl_en)
        {
            /*if acl disable, clear associated config*/
            SetDsDestPort(V, gAcl_0_aclLabel_f + acl_priority*step,             &ds_dest_port, 0);
            SetDsDestPort(V, gAcl_0_aclUseGlobalPortType_f + acl_priority*step, &ds_dest_port, 0);
            SetDsDestPort(V, gAcl_0_aclUsePIVlan_f + acl_priority*step,         &ds_dest_port, 0);
            SetDsDestPort(V, gAcl_0_aclLookupType_f + acl_priority*step,        &ds_dest_port, 0);
        }
        else
        {
            SetDsDestPort(V, gAcl_0_aclLookupType_f + acl_priority*step,        &ds_dest_port, sys_lkup_type);
            SetDsDestPort(V, gAcl_0_aclLabel_f + acl_priority*step,             &ds_dest_port, p_prop->class_id);
            SetDsDestPort(V, gAcl_0_aclUseGlobalPortType_f + acl_priority*step, &ds_dest_port, gport_type);
            SetDsDestPort(V, gAcl_0_aclUsePIVlan_f + acl_priority*step,         &ds_dest_port,
                                                CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN)?1:0);
        }
        /*write hw*/
        cmd = DRV_IOW(DsDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip,lport,cmd,&ds_dest_port));
    }
    return CTC_E_NONE;
}

int32
sys_usw_port_get_acl_property(uint8 lchip, uint32 gport, ctc_acl_property_t* p_prop)
{
    uint8  acl_priority = 0;
    uint16 lport = 0;
    uint32 cmd = 0;
    uint32 step = 0;
    uint8  gport_type = 0;
    uint8  sys_lkup_type = 0;
    uint8  use_mapped_vlan = 0;
    uint8  use_wlan = 0;

    DsSrcPort_m ds_src_port;
    DsDestPort_m ds_dest_port;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    CTC_PTR_VALID_CHECK(p_prop);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    CTC_MAX_VALUE_CHECK(p_prop->direction, CTC_EGRESS);

    if (CTC_FLAG_ISSET(p_prop->flag, CTC_ACL_PROP_FLAG_USE_HASH_LKUP))
    {
        cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ds_src_port));

        p_prop->hash_field_sel_id = GetDsSrcPort(V, aclFlowHashFieldSel_f,&ds_src_port);
        p_prop->hash_lkup_type = GetDsSrcPort(V, aclFlowHashType_f,&ds_src_port);
        p_prop->flex_key_en = GetDsSrcPort(V, aclFlowHashXKeyEn_f,&ds_src_port);
        if(GetDsSrcPort(V, flowHashUsePiVlan_f,&ds_src_port))
        {
            CTC_SET_FLAG(p_prop->flag,CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN);
        }
        p_prop->acl_en = p_prop->hash_lkup_type ? 1 : 0;

        return CTC_E_NONE;
    }

    acl_priority = p_prop->acl_priority;
    if(p_prop->direction == CTC_INGRESS)
    {
        CTC_MAX_VALUE_CHECK(acl_priority, MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM)-1);
        cmd = DRV_IOR(DsSrcPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip,lport,cmd,&ds_src_port));

        DRV_GET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclLabel", &ds_src_port, p_prop->class_id, "_0_", acl_priority);
        DRV_GET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclUseGlobalPortType", &ds_src_port, gport_type, "_0_", acl_priority);
        DRV_GET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclUsePIVlan", &ds_src_port, use_mapped_vlan, "_0_", acl_priority);
        DRV_GET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclLookupType", &ds_src_port, sys_lkup_type, "_0_", acl_priority);
        DRV_GET_FLD_V2(lchip, DsSrcPort_t, "gAcl_0_aclUseCapwapInfo", &ds_src_port, use_wlan, "_0_", acl_priority);
    }
    else
    {
        CTC_MAX_VALUE_CHECK(acl_priority, MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM)-1);
        step = DsDestPort_gAcl_1_aclLookupType_f - DsDestPort_gAcl_0_aclLookupType_f;
        cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip,lport,cmd,&ds_dest_port));

        sys_lkup_type = GetDsDestPort(V,gAcl_0_aclLookupType_f + acl_priority*step,          &ds_dest_port);
        gport_type    = GetDsDestPort(V,gAcl_0_aclUseGlobalPortType_f + acl_priority*step,   &ds_dest_port);
        p_prop->class_id = GetDsDestPort(V,gAcl_0_aclLabel_f + acl_priority*step,            &ds_dest_port);
        use_mapped_vlan = GetDsDestPort(V,gAcl_0_aclUsePIVlan_f + acl_priority*step,         &ds_dest_port);
    }
    if (DRV_FROM_AT(lchip))
    {
        DsSrcPortAclCtl_m ds_src_port_acl;
        DsDestPortAclCtl_m ds_dest_port_acl;
        if (CTC_INGRESS == p_prop->direction )
        {
            CTC_MAX_VALUE_CHECK(acl_priority, MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM)-1);
            step = DsSrcPortAclCtl_gAcl_1_aclLookupType_f - DsSrcPortAclCtl_gAcl_0_aclLookupType_f;
            cmd = DRV_IOR(DsSrcPortAclCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip,lport,cmd,&ds_src_port_acl));

            sys_lkup_type = GetDsSrcPortAclCtl(V, gAcl_0_aclLookupType_f + acl_priority*step,          &ds_src_port_acl);
            gport_type    = GetDsSrcPortAclCtl(V, gAcl_0_aclUseGlobalPortType_f + acl_priority*step,   &ds_src_port_acl);
            p_prop->class_id = GetDsSrcPortAclCtl(V, gAcl_0_aclLabel_f + acl_priority*step,            &ds_src_port_acl);
            use_mapped_vlan = GetDsSrcPortAclCtl(V, gAcl_0_aclUsePIVlan_f + acl_priority*step,         &ds_src_port_acl);
        }
        else
        {
            CTC_MAX_VALUE_CHECK(acl_priority, MCHIP_CAP(SYS_CAP_ACL_EGRESS_LKUP_NUM)-1);
            step = DsDestPortAclCtl_gAcl_1_aclLookupType_f - DsDestPortAclCtl_gAcl_0_aclLookupType_f;
            cmd = DRV_IOR(DsDestPortAclCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip,lport,cmd,&ds_dest_port_acl));

            sys_lkup_type = GetDsDestPortAclCtl(V, gAcl_0_aclLookupType_f + acl_priority*step,          &ds_dest_port_acl);
            gport_type    = GetDsDestPortAclCtl(V, gAcl_0_aclUseGlobalPortType_f + acl_priority*step,   &ds_dest_port_acl);
            p_prop->class_id = GetDsDestPortAclCtl(V, gAcl_0_aclLabel_f + acl_priority*step,            &ds_dest_port_acl);
            use_mapped_vlan = GetDsDestPortAclCtl(V, gAcl_0_aclUsePIVlan_f + acl_priority*step,         &ds_dest_port_acl);
        }
    }

    p_prop->acl_en = sys_lkup_type ? 1 : 0;
    p_prop->tcam_lkup_type  = sys_usw_unmap_acl_tcam_lkup_type(lchip, sys_lkup_type);
    if(use_mapped_vlan)
    {
        CTC_SET_FLAG(p_prop->flag, CTC_ACL_PROP_FLAG_USE_MAPPED_VLAN);
    }
    if(use_wlan)
    {
        CTC_SET_FLAG(p_prop->flag, CTC_ACL_PROP_FLAG_USE_WLAN);
    }

    if(gport_type == DRV_ENUM(DRV_FLOWPORTTYPE_BITMAP))
    {
        CTC_SET_FLAG(p_prop->flag, CTC_ACL_PROP_FLAG_USE_PORT_BITMAP);
    }
    else if(gport_type == DRV_ENUM(DRV_FLOWPORTTYPE_LPORT))
    {
        CTC_SET_FLAG(p_prop->flag, CTC_ACL_PROP_FLAG_USE_LOGIC_PORT);
    }
    else if(gport_type == DRV_ENUM(DRV_FLOWPORTTYPE_METADATA))
    {
        CTC_SET_FLAG(p_prop->flag, CTC_ACL_PROP_FLAG_USE_METADATA);
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_acl_property(uint8 lchip, uint32 gport, ctc_acl_property_t* p_prop, uint8 block_num, uint8 *block_list)
{
    uint8  loop = 0;
    uint16 lport = 0;
    uint8* acl_block_list = block_list;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    for (loop=0; loop<block_num; loop++)
    {
        p_prop->acl_priority = acl_block_list[loop];
        CTC_ERROR_RETURN(_sys_usw_port_set_acl_property(lchip, lport, p_prop));
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_acl_league_property(uint8 lchip, uint8 acl_pri, uint8 enable, uint8 sub_blk_cnt, uint8 *sub_blk_list)
{
    uint16 loop = 0;
    uint8  index = 0;
    uint8  gchip_id = 0;
    uint32 gport = 0;
    ctc_acl_property_t acl_prop;
    uint8  acl_block_base = (acl_pri>=MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM))?(MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM)):(0);
    uint8  dir = (acl_pri>=MCHIP_CAP(SYS_CAP_ACL_INGRESS_LKUP_NUM))?(CTC_EGRESS):(CTC_INGRESS);

    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip_id));
    for (loop=0; loop<MCHIP_CAP(SYS_CAP_PER_SLICE_PORT_NUM); loop++)
    {
        sal_memset(&acl_prop, 0, sizeof(ctc_acl_property_t));
        acl_prop.direction = dir;
        gport = SYS_MAP_DRV_LPORT_TO_CTC_GPORT(gchip_id, loop);
        acl_prop.acl_priority = acl_pri - acl_block_base;
        acl_prop.acl_en = 0;
        CTC_ERROR_RETURN(sys_usw_port_get_acl_property(lchip, gport, &acl_prop));
        if (0 != acl_prop.acl_en)
        {
            for (index=0; index<sub_blk_cnt; index++)
            {
                acl_prop.acl_priority = sub_blk_list[index] - acl_block_base;
                acl_prop.acl_en = enable;
                CTC_ERROR_RETURN(_sys_usw_port_set_acl_property(lchip, loop, &acl_prop));
            }
        }
    }
    return CTC_E_NONE;
}

int32
sys_usw_port_set_bpe_property(uint8 lchip, uint32 gport, ctc_port_bpe_property_t* p_prop)
{
    uint32 cmd = 0;
    uint32 chan_id = 0;
    uint32 table_index = 0;
    uint16 lport = 0;
    uint32 src_mux_type = 0;
    uint32 dst_mux_type = 0;
    uint32 ecid = 0;
    uint32 name_space = 0;
    uint32 hash1_type = 0;
    uint32 hash2_type = 0;
    uint32 pause_bypass =0;
    sys_port_info_t port_info;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    CTC_MAX_VALUE_CHECK(p_prop->name_space, SYS_PORT_BPE_MAX_NAME_SPACE);
    CTC_MAX_VALUE_CHECK(p_prop->ecid, SYS_PORT_BPE_MAX_ECID);

    sal_memset(&port_info, 0 ,sizeof(sys_port_info_t));

    /*get channel from port */
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
    if (!SYS_IS_NETWORK_CHANNEL(chan_id))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;
    }

    if (DRV_FROM_AT(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, 0, &port_info));
        lchip = SYS_PP_BASE(lchip) + port_info.pp_id;
        table_index = port_info.sub_chan_id;
    }
    else
    {
        table_index = chan_id;
    }

    switch(p_prop->extend_type)
    {
    case CTC_PORT_BPE_EXTEND_TYPE_NONE:
        src_mux_type = 0;
        dst_mux_type = 0;
        ecid = 0;
        name_space =  0;
        hash1_type = 0;
        hash2_type = 0;
        pause_bypass = 0;
        CTC_ERROR_RETURN(sys_usw_port_set_property(lchip, gport, CTC_PORT_PROP_ADD_DEFAULT_VLAN_DIS, 0));
        break;
    case CTC_PORT_BPE_8021BR_PE_EXTEND:
        CTC_MIN_VALUE_CHECK(p_prop->ecid, 1);
        src_mux_type = 0;
        dst_mux_type = 0;
        ecid = p_prop->ecid;
        name_space =  0;
        hash1_type = 0;
        hash2_type = 0;
        pause_bypass = 1;
        CTC_ERROR_RETURN(sys_usw_port_set_property(lchip, gport, CTC_PORT_PROP_ADD_DEFAULT_VLAN_DIS, 1));

        break;
    case CTC_PORT_BPE_8021BR_PE_CASCADE:
        src_mux_type = BPE_IGS_MUXTYPE_PE_DOWNLINK_WITH_CASCADE_PORT;
        dst_mux_type = BPE_EGS_MUXTYPE_CASCADE;
        ecid = 0;
        name_space =  p_prop->name_space;
        hash1_type = DRV_ENUM(DRV_USERIDPORTHASHTYPE_ECIDNAMESPACE);
        hash2_type = DRV_ENUM(DRV_USERIDPORTHASHTYPE_INGECIDNAMESPACE);
        pause_bypass = 0;

        break;
    case CTC_PORT_BPE_8021BR_PE_UPSTREAM:
        src_mux_type = BPE_IGS_MUXTYPE_PE_UPLINK;
        dst_mux_type = BPE_EGS_MUXTYPE_UPSTREAM;
        ecid = 0;
        name_space =  p_prop->name_space;
        hash1_type = DRV_ENUM(DRV_USERIDPORTHASHTYPE_ECIDNAMESPACE);
        hash2_type = DRV_ENUM(DRV_USERIDPORTHASHTYPE_INGECIDNAMESPACE);
        pause_bypass = 0;

        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    cmd = DRV_IOW(DsChannelizeMode_t, DsChannelizeMode_pauseByPass_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, table_index, DRV_CMD_DP_EN(cmd, port_info.dp_id) , &pause_bypass));

    cmd = DRV_IOW(IpeHeaderAdjustPhyPortMap_t, IpeHeaderAdjustPhyPortMap_ecidNameSpace_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &name_space));

    cmd = DRV_IOW(DsPortLinkAgg_t, DsPortLinkAgg_ecid_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &ecid));

    cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_userIdPortHash1Type_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &hash1_type));

    cmd = DRV_IOW(DsPhyPortExt_t, DsPhyPortExt_userIdPortHash2Type_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &hash2_type));

    if(DRV_FROM_TMM(lchip))
    {
            cmd = DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_userIdPortHash0Type_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &hash1_type));
            cmd = DRV_IOW(DsPhyPortExt2_t, DsPhyPortExt2_userIdPortHash1Type_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &hash2_type));
    }
    /* cfg mux type */
    cmd = DRV_IOW(IpePhyPortMuxCtl_t, IpePhyPortMuxCtl_muxType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &src_mux_type));

    cmd = DRV_IOW(DsDestPort_t, DsDestPort_muxPortType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &dst_mux_type));


    return CTC_E_NONE;
}

int32
sys_usw_port_get_bpe_property(uint8 lchip, uint32 gport, ctc_port_bpe_property_t* p_prop)
{
    uint32 cmd = 0;
    uint32 chan_id = 0;
    uint16 lport = 0;
    uint32 src_mux_type = 0;
    uint32 ecid = 0;
    uint32 name_space = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    sal_memset(p_prop, 0, sizeof(ctc_port_bpe_property_t));

    /*get channel from port */
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &chan_id));
    if (!SYS_IS_NETWORK_CHANNEL(chan_id))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;
    }


    cmd = DRV_IOR(IpeHeaderAdjustPhyPortMap_t, IpeHeaderAdjustPhyPortMap_ecidNameSpace_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &name_space));

    cmd = DRV_IOR(DsPortLinkAgg_t, DsPortLinkAgg_ecid_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &ecid));

    /* cfg mux type */
    cmd = DRV_IOR(IpePhyPortMuxCtl_t, IpePhyPortMuxCtl_muxType_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, chan_id, cmd, &src_mux_type));

    switch(src_mux_type)
    {
    case BPE_IGS_MUXTYPE_PE_DOWNLINK_WITH_CASCADE_PORT:
        p_prop->extend_type = CTC_PORT_BPE_8021BR_PE_CASCADE;
        p_prop->name_space = name_space;
        break;

    case BPE_IGS_MUXTYPE_PE_UPLINK:
        p_prop->extend_type = CTC_PORT_BPE_8021BR_PE_UPSTREAM;
        p_prop->name_space = name_space;
        break;


    case BPE_IGS_MUXTYPE_NOMUX:
        if (ecid)
        {
            p_prop->extend_type = CTC_PORT_BPE_8021BR_PE_EXTEND;
            p_prop->ecid = ecid;
        }
        else
        {
            p_prop->extend_type = CTC_PORT_BPE_EXTEND_TYPE_NONE;
        }
        break;

    default:
        return CTC_E_INVALID_PARAM;
    }


    return CTC_E_NONE;
}

int32
sys_usw_port_register_rchip_get_gport_idx_cb(uint8 lchip, SYS_PORT_GET_RCHIP_GPORT_IDX_CB cb)
{
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    p_usw_port_master[lchip]->rchip_gport_idx_cb  = cb;

    return CTC_E_NONE;
}

int32
sys_usw_port_set_mac_auth(uint8 lchip, uint32 gport, bool enable)
{
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    if (DRV_IS_DUET2(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_port_set_property(lchip, gport, CTC_PORT_PROP_SRC_MISMATCH_EXCEPTION_EN, enable));
        CTC_ERROR_RETURN(sys_usw_port_set_internal_property(lchip, gport, SYS_PORT_PROP_SECURITY_EN, enable));
    }
    else
    {
        CTC_ERROR_RETURN(sys_usw_port_set_internal_property(lchip, gport, SYS_PORT_PROP_MAC_AUTH_EN, enable));
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_get_mac_auth(uint8 lchip, uint32 gport, bool* enable)
{
    uint32 value1 = 0;
    uint32 value2 = 0;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    if (DRV_IS_DUET2(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_port_get_property(lchip, gport, CTC_PORT_PROP_SRC_MISMATCH_EXCEPTION_EN, &value1));
        CTC_ERROR_RETURN(sys_usw_port_get_internal_property(lchip, gport, SYS_PORT_PROP_SECURITY_EN, &value2));

        *enable = ((value1 & value2) == 1) ? TRUE : FALSE;
    }
    else
    {
        CTC_ERROR_RETURN(sys_usw_port_get_internal_property(lchip, gport, SYS_PORT_PROP_MAC_AUTH_EN, &value1));
        *enable = (value1 == 1) ? TRUE : FALSE;
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_flow_ctl_en(uint8 lchip, void* p_fc_prop, uint8 is_recover)
{
    int32 ret = CTC_E_NONE;

    if (!DRV_FROM_TMM(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_mac_set_flow_ctl_en(lchip, p_fc_prop));
        return ret;
    }
    if (MCHIP_PORT(lchip)->port_set_flow_ctl_en)
    {
        ret = MCHIP_PORT(lchip)->port_set_flow_ctl_en(lchip, (void *)p_fc_prop, is_recover);
    }

    return ret;
}

int32
sys_usw_port_get_flow_ctl_en(uint8 lchip, void* p_fc_prop)
{
    int32 ret = CTC_E_NONE;

    if (!DRV_FROM_TMM(lchip))
    {
        CTC_ERROR_RETURN(sys_usw_mac_get_flow_ctl_en(lchip, p_fc_prop));
        return ret;
    }
    if (MCHIP_PORT(lchip)->port_get_flow_ctl_en)
    {
        ret = MCHIP_PORT(lchip)->port_get_flow_ctl_en(lchip, (void *)p_fc_prop);
    }

    return ret;
}

int32
sys_usw_port_set_port_swap(uint8 lchip, uint32 src_gport, uint32 dst_gport)
{
    uint16 src_lport = 0;
    uint16 dst_lport = 0;
    uint32 port_chan_id = 0;
    uint32 port_pchan_id = 0;
    uint8 gchip = SYS_MAP_CTC_GPORT_TO_GCHIP(dst_gport);
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    if(src_gport == dst_gport )
    {
        return CTC_E_INVALID_CONFIG;
    }
    if (!sys_usw_chip_is_local(lchip, gchip))
    {
        return CTC_E_NONE;
    }
    src_lport = CTC_MAP_GPORT_TO_LPORT(src_gport);
    dst_lport = CTC_MAP_GPORT_TO_LPORT(dst_gport);
    if(src_lport >= MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP) || dst_lport >= MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP))
    {
        return CTC_E_INVALID_PORT;
    }
    dmps_port_info.gport = src_gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &port_chan_id));
    dmps_port_info.gport = dst_gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &port_pchan_id));
    CTC_ERROR_RETURN(sys_usw_dmps_port_swap(lchip, src_lport, dst_lport));
    CTC_ERROR_RETURN(sys_usw_add_port_to_channel(lchip, src_lport, port_pchan_id, 0));
    CTC_ERROR_RETURN(sys_usw_add_port_to_channel(lchip, dst_lport, port_chan_id, 0));

    return CTC_E_NONE;
}

/*value, 0:flow 1: inner 2: outer*/
int32
_sys_usw_port_map_flow_value(uint8 lchip, uint32 value, uint8* enable, uint8* valid)
{
    if (0 == value )
    {
        *enable = 0;
        *valid = 0;
    }
    else if (1 == value )
    {
        *enable = 0;
        *valid = 1;
    }
    else if (2 == value )
    {
        *enable = 1;
        *valid = 1;
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
_sys_usw_port_unmap_flow_value(uint8 lchip, uint8 enable, uint8 valid, uint32* p_value)
{
    if ((0 == enable) && (0 == valid))
    {
        *p_value = 0;
    }
    else if ((0 == enable) && (1 == valid))
    {
        *p_value = 1;
    }
    else if ((1 == enable) && (1 == valid))
    {
        *p_value = 2;
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_usw_port_set_logic_port_property(uint8 lchip,uint32 logic_port,ctc_logic_port_property_t logic_port_prop,ctc_direction_t dir,void* p_value)
{
    sys_ldp_t ldp;
    sys_scl_type_para_t scl_type_para;
    ctc_logic_port_scl_property_t* p_lp_scl = NULL;
    uint32 value = 0;
    uint8 enable = 0;
    uint8 valid = 0;
    int32 ret = CTC_E_NONE;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "Set Logic port %d property %d direction %d\n", logic_port, logic_port_prop, dir);

    CTC_PTR_VALID_CHECK(p_value);
    CTC_MAX_VALUE_CHECK(logic_port, MCHIP_CAP(SYS_CAP_MAX_LOGIC_PORT));

    if (CTC_INGRESS == dir)
    {
        return CTC_E_NOT_SUPPORT;
    }

    sal_memset(&ldp, 0, sizeof(ldp));
    if((CTC_EGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        CTC_ERROR_RETURN(sys_usw_nh_get_logic_port_type(lchip, logic_port, &ldp, TRUE));
        switch(logic_port_prop)
        {
            case CTC_LOGIC_PORT_PROP_GRP_ID:
                value = *((uint32*)p_value);
                
                if (0 != ldp.esid)
                {
                    CTC_MAX_VALUE_CHECK(value, 0xFF);/*enable esid logic dest port only support 0xFF*/
                }
                else
                {
                    CTC_MAX_VALUE_CHECK(value, SYS_LP_GRP_ID_MAX);
                }
                ldp.lp_grp_id = value;
                break;   

            case CTC_LOGIC_PORT_PROP_ISOLATION_ID:
                value = *((uint32*)p_value);
                CTC_MAX_VALUE_CHECK(value, SYS_ISOLATION_ID_MAX);
                ldp.isolation_id = value;
                break;
            
            case CTC_LOGIC_PORT_PROP_SCL_EN:
                p_lp_scl = (ctc_logic_port_scl_property_t*)p_value;
                if(p_lp_scl->hash_type > (CTC_PORT_EGS_SCL_HASH_TYPE_MAX-1)
                  || (p_lp_scl->scl_id > 1))
                {
                    return CTC_E_INVALID_PARAM;
                }
                if (p_lp_scl->flex_key_en)
                {
                    ldp.nsh_en = 1;
                }
                else
                {
                    sal_memset(&scl_type_para, 0, sizeof(sys_scl_type_para_t));
                    scl_type_para.ctc_hash_type = p_lp_scl->hash_type;
                    CTC_ERROR_RETURN(_sys_usw_port_map_scl_type(lchip, CTC_EGRESS, &scl_type_para));
                    if (0 == p_lp_scl->scl_id)
                    {
                        ldp.scl0_hash_type = scl_type_para.drv_hash_type;
                    }
                    else
                    {
                        ldp.scl1_hash_type = scl_type_para.drv_hash_type;
                    }
                }
                break;

            case CTC_LOGIC_PORT_PROP_ACL_LKUP_BY_OUTER_HEAD:
                value = *((uint32*)p_value);
                CTC_ERROR_RETURN(_sys_usw_port_map_flow_value(lchip, value, &enable, &valid));
                ldp.acl_use_outer_valid = valid;
                ldp.acl_use_outer = enable;
                break;
            case CTC_LOGIC_PORT_PROP_ACL_AWARE_TUNNEL_INFO_EN:
                value = *((uint32*)p_value);
                CTC_ERROR_RETURN(_sys_usw_port_map_flow_value(lchip, value, &enable, &valid));
                ldp.acl_merge_valid = valid;
                ldp.acl_merge = enable;
                break;
            case CTC_LOGIC_PORT_PROP_IPFIX_LKUP_BY_OUTER_HEAD:
                value = *((uint32*)p_value);
                CTC_ERROR_RETURN(_sys_usw_port_map_flow_value(lchip, value, &enable, &valid));
                ldp.ipfix_use_outer_valid = valid;
                ldp.ipfix_use_outer = enable;
                break;

            case CTC_LOGIC_PORT_PROP_ESID:
                value = *((uint32*)p_value);
                CTC_MAX_VALUE_CHECK(value, SYS_PORT_MAX_ESID);
                ldp.esid = value;
                break;

            default:
                return CTC_E_INVALID_PARAM;
                break;
        }
        CTC_ERROR_RETURN(sys_usw_nh_set_logic_port_type(lchip, logic_port, &ldp, TRUE));
    }

    return ret;
}

int32
sys_usw_port_get_logic_port_property(uint8 lchip,uint32 logic_port,ctc_logic_port_property_t logic_port_prop,ctc_direction_t dir,void* p_value)
{
    sys_ldp_t ldp;
    sys_scl_type_para_t scl_type_para;
    ctc_logic_port_scl_property_t* p_lp_scl = NULL;
    int32 ret = CTC_E_NONE;

    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_PARAM, "Get Logic port %d property %d direction %d\n", logic_port, logic_port_prop, dir);

    CTC_PTR_VALID_CHECK(p_value);
    CTC_MAX_VALUE_CHECK(logic_port, MCHIP_CAP(SYS_CAP_MAX_LOGIC_PORT));

    if (CTC_INGRESS == dir)
    {
        return CTC_E_NOT_SUPPORT;
    }

    sal_memset(&ldp, 0, sizeof(ldp));
    if((CTC_EGRESS == dir) || (CTC_BOTH_DIRECTION == dir))
    {
        CTC_ERROR_RETURN(sys_usw_nh_get_logic_port_type(lchip, logic_port, &ldp, TRUE));
        switch(logic_port_prop)
        {
            case CTC_LOGIC_PORT_PROP_GRP_ID:
                *((uint32*)p_value) = ldp.lp_grp_id;
                break;   
            
            case CTC_LOGIC_PORT_PROP_ISOLATION_ID:
                *((uint32*)p_value) = ldp.isolation_id;
                break;
            
            case CTC_LOGIC_PORT_PROP_SCL_EN:
                p_lp_scl = (ctc_logic_port_scl_property_t*)p_value;
                if(p_lp_scl->scl_id > 1)
                {
                    return CTC_E_INVALID_PARAM;
                }
                p_lp_scl->flex_key_en = ldp.nsh_en;
                if (0 == p_lp_scl->flex_key_en)
                {
                    sal_memset(&scl_type_para, 0, sizeof(sys_scl_type_para_t));
                    scl_type_para.drv_hash_type = (0 == p_lp_scl->scl_id)?ldp.scl0_hash_type:ldp.scl1_hash_type;
                    CTC_ERROR_RETURN(_sys_usw_port_unmap_scl_type(lchip, CTC_EGRESS, &scl_type_para));
                    p_lp_scl->hash_type = scl_type_para.ctc_hash_type;
                }
                break;

            case CTC_LOGIC_PORT_PROP_ACL_LKUP_BY_OUTER_HEAD:
                CTC_ERROR_RETURN(_sys_usw_port_unmap_flow_value(lchip, ldp.acl_use_outer, ldp.acl_use_outer_valid, p_value));
                break;

            case CTC_LOGIC_PORT_PROP_ACL_AWARE_TUNNEL_INFO_EN:
                CTC_ERROR_RETURN(_sys_usw_port_unmap_flow_value(lchip, ldp.acl_merge, ldp.acl_merge_valid, p_value));
                break;

            case CTC_LOGIC_PORT_PROP_IPFIX_LKUP_BY_OUTER_HEAD:
                CTC_ERROR_RETURN(_sys_usw_port_unmap_flow_value(lchip, ldp.ipfix_use_outer, ldp.ipfix_use_outer_valid, p_value));
                break;

            case CTC_LOGIC_PORT_PROP_ESID:
                *((uint32*)p_value) = ldp.esid;
                break;
            default:
                return CTC_E_INVALID_PARAM;
                break;
        }
    }

    return ret;
}

int32 sys_usw_port_get_ptp_domain(uint8 lchip, uint16 lport, uint8* domain_id)
{
    *domain_id = p_usw_port_master[lchip]->port_prop[lport].ptp_domain_id;
    return CTC_E_NONE;
}

int32 sys_usw_port_wb_sync(uint8 lchip, uint32 app_id)
{
    uint32 loop = 0;
    int32 ret = CTC_E_NONE;
    ctc_wb_data_t wb_data = {0};
    sys_wb_port_master_t* port_master = NULL;
    sys_wb_port_prop_t   port_prop;
    uint32  max_entry_cnt = 0;

    sal_memset(&port_prop, 0, sizeof(port_prop));

    CTC_WB_ALLOC_BUFFER(&wb_data.buffer);
    if (app_id == 0 || CTC_WB_SUBID(app_id) == SYS_WB_APPID_PORT_SUBID_MASTER)
    {
        CTC_WB_INIT_DATA_T((&wb_data), sys_wb_port_master_t, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_MASTER);
        /*mapping data*/
        port_master = (sys_wb_port_master_t *) wb_data.buffer;
        port_master->lchip = lchip;
        port_master->igs_isloation_bitmap = p_usw_port_master[lchip]->igs_isloation_bitmap[0];
        port_master->igs_isloation_bitmap1 = p_usw_port_master[lchip]->igs_isloation_bitmap[1];
        sal_memcpy(port_master->tx_frame_ref_cnt, p_usw_port_master[lchip]->tx_frame_ref_cnt, SYS_PORT_TX_MAX_FRAME_SIZE_NUM);
        port_master->version = SYS_WB_VERSION_PORT;
        port_master->internal_port_start = p_usw_port_master[lchip]->internal_port_start;
        wb_data.valid_cnt = 1;
        CTC_ERROR_GOTO(ctc_wb_add_entry(&wb_data), ret, done);
        CTC_WB_SYNC_END_DATA(CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_MASTER);
    }

    if (app_id == 0 || CTC_WB_SUBID(app_id) == SYS_WB_APPID_PORT_SUBID_PROP)
    {
        CTC_WB_INIT_DATA_T((&wb_data), sys_wb_port_prop_t, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP);
        max_entry_cnt =  wb_data.buffer_len / (wb_data.key_len + wb_data.data_len);
        do
        {
            port_prop.lport = loop;
            port_prop.lbk_en = p_usw_port_master[lchip]->port_prop[loop].lbk_en;
            port_prop.subif_en = p_usw_port_master[lchip]->port_prop[loop].subif_en;
            port_prop.xfabric_type = p_usw_port_master[lchip]->port_prop[loop].xfabric_type;
            port_prop.xpipe_type = p_usw_port_master[lchip]->port_prop[loop].xpipe_type;
            port_prop.is_mac_da = p_usw_port_master[lchip]->port_prop[loop].is_mac_da;
            port_prop.inter_lport = p_usw_port_master[lchip]->port_prop[loop].inter_lport;
            port_prop.nhid = p_usw_port_master[lchip]->port_prop[loop].nhid;
            port_prop.network_port = p_usw_port_master[lchip]->network_port[loop];
            sal_memcpy((uint8*)wb_data.buffer + wb_data.valid_cnt * sizeof(sys_wb_port_prop_t),  (uint8*)&port_prop, sizeof(sys_wb_port_prop_t));
            if (++wb_data.valid_cnt == max_entry_cnt)
            {
                CTC_ERROR_GOTO(ctc_wb_add_entry(&wb_data), ret, done);
                wb_data.valid_cnt = 0;
                break;
            }
        }
        while (++loop < SYS_USW_MAX_PORT_NUM_PER_CHIP);

        if (wb_data.valid_cnt)
        {
            CTC_ERROR_GOTO(ctc_wb_add_entry(&wb_data), ret, done);
        }
        CTC_WB_SYNC_END_DATA(CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP);
    }

    if (app_id == 0 || CTC_WB_SUBID(app_id) == SYS_WB_APPID_INTERPORT_SUBID_MASTER )
    {
        CTC_ERROR_GOTO(sys_usw_internal_port_wb_sync(lchip, app_id),ret, done);
    }

    if (CTC_WB_SUBID(app_id) == SYS_WB_APPID_INTERPORT_SUBID_USED )
    {
        CTC_ERROR_GOTO(sys_usw_internal_port_wb_sync(lchip, app_id),ret, done);
    }

    if (app_id == 0 || CTC_WB_SUBID(app_id) == SYS_WB_APPID_PORT_SUBID_MAC_PROP )
    {
        CTC_ERROR_GOTO(sys_usw_mac_wb_sync(lchip, app_id),ret, done);
    }

    done:
    CTC_WB_FREE_BUFFER(wb_data.buffer);

    return ret;
}

int32 sys_usw_port_wb_restore(uint8 lchip)
{
    uint32 loop_cnt = 0;
    int32 ret = CTC_E_NONE;
    ctc_wb_query_t    wb_query;

    sys_wb_port_master_t  wb_port_master;
    sys_wb_port_prop_t    wb_port_prop;

    sys_wb_port_master_t* p_wb_port_master = &wb_port_master;
    sys_wb_port_prop_t* p_wb_port_prop = &wb_port_prop;
    uint32 entry_cnt = 0;
    uint32 lport = 0;
    sys_usw_opf_t opf;
    uint32  cmd = 0;
    uint32  field_val = 0;
    uint32  port_sflow = 0;
    uint32   loop = 0;
    uint8 step = 0;
    uint32 mac_id = 0;
    sys_usw_dmps_port_info_t dmps_port_info;
    ds_t ds;
    uint8 rtc_id = 0;
    DsDestPort_m dest_port;

    sal_memset(&dmps_port_info, 0, sizeof(sys_usw_dmps_port_info_t));
    sal_memset(&ds, 0, sizeof(ds));

    /*restore port property*/
    CTC_WB_ALLOC_BUFFER(&wb_query.buffer);

    CTC_WB_INIT_QUERY_T((&wb_query),sys_wb_port_master_t, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_MASTER);

    /*set default value*/
    sal_memset(&wb_port_master, 0, sizeof(wb_port_master));
    CTC_WB_QUERY_ENTRY_BEGIN((&wb_query));
        sal_memcpy((uint8*)p_wb_port_master, (uint8*)(wb_query.buffer) + entry_cnt * (wb_query.key_len + wb_query.data_len), wb_query.key_len + wb_query.data_len);
        entry_cnt++;

        if (CTC_WB_VERSION_CHECK(SYS_WB_VERSION_PORT, p_wb_port_master->version))
        {
            ret = CTC_E_VERSION_MISMATCH;
            goto done;
        }
        p_usw_port_master[lchip]->igs_isloation_bitmap[0] = p_wb_port_master->igs_isloation_bitmap;
        p_usw_port_master[lchip]->igs_isloation_bitmap[1] = p_wb_port_master->igs_isloation_bitmap1;
        p_usw_port_master[lchip]->internal_port_start = p_wb_port_master->internal_port_start;
        MCHIP_CAP(SYS_CAP_INTERNAL_PORT_START) = p_wb_port_master->internal_port_start;
        sal_memcpy(p_usw_port_master[lchip]->tx_frame_ref_cnt, p_wb_port_master->tx_frame_ref_cnt, SYS_PORT_TX_MAX_FRAME_SIZE_NUM);

    if (DRV_FROM_TM(lchip))
    {
        sal_memset(&opf, 0, sizeof(sys_usw_opf_t));
        opf.pool_type = p_usw_port_master[lchip]->opf_type_port_sflow;
        loop_cnt = DRV_FROM_TMM(lchip) ? MCHIP_CAP(SYS_CAP_SPEC_MAX_PORT_NUM) : MCHIP_CAP(SYS_CAP_PHY_PORT_NUM_PER_SLICE);
        for (loop=0; loop<loop_cnt; loop++)
        {
            /*restore ingress port sflow*/
            cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_randomLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, loop, cmd, &field_val));
            if (field_val)
            {
                opf.pool_index = CTC_INGRESS;
                cmd = DRV_FROM_TMM(lchip) ? DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_randomSeedId_f) : DRV_IOR(IpeRandomSeedMap_t, IpeRandomSeedMap_seedId_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, loop, cmd, &port_sflow));
                if(port_sflow)
                {
                    sys_usw_opf_alloc_offset_from_position(lchip, &opf, 1, port_sflow);
                }
            }
            /*restore egress port sflow*/
            cmd = DRV_IOR(DsDestPort_t, DsDestPort_randomLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, loop, cmd, &field_val));
            if (field_val)
            {
                opf.pool_index = CTC_EGRESS;
                cmd = DRV_FROM_TMM(lchip) ? DRV_IOR(DsDestPort_t, DsDestPort_randomSeedId_f) : DRV_IOR(EpeRandomSeedMap_t, EpeRandomSeedMap_seedId_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, loop, cmd, &port_sflow));
                if(port_sflow)
                {
                    sys_usw_opf_alloc_offset_from_position(lchip, &opf, 1, port_sflow);
                }
            }
        }
    }

    CTC_WB_QUERY_ENTRY_END((&wb_query));

    CTC_WB_INIT_QUERY_T((&wb_query),sys_wb_port_prop_t, CTC_FEATURE_PORT, SYS_WB_APPID_PORT_SUBID_PROP);

    /*set default value*/
    sal_memset(&wb_port_prop, 0, sizeof(wb_port_prop));

    CTC_WB_QUERY_ENTRY_BEGIN((&wb_query));
        sal_memcpy((uint8*)p_wb_port_prop, (uint8*)(wb_query.buffer) + entry_cnt * (wb_query.key_len + wb_query.data_len), wb_query.key_len + wb_query.data_len);
        entry_cnt++;

        lport = p_wb_port_prop->lport;
        p_usw_port_master[lchip]->port_prop[lport].lbk_en = p_wb_port_prop->lbk_en;
        p_usw_port_master[lchip]->port_prop[lport].subif_en = p_wb_port_prop->subif_en;
        p_usw_port_master[lchip]->port_prop[lport].xfabric_type = p_wb_port_prop->xfabric_type;
        p_usw_port_master[lchip]->port_prop[lport].xpipe_type = p_wb_port_prop->xpipe_type;
        p_usw_port_master[lchip]->port_prop[lport].is_mac_da = p_wb_port_prop->is_mac_da;
        p_usw_port_master[lchip]->port_prop[lport].inter_lport = p_wb_port_prop->inter_lport;
        p_usw_port_master[lchip]->port_prop[lport].nhid = p_wb_port_prop->nhid;
        p_usw_port_master[lchip]->port_prop[lport].rsv = 0;
        p_usw_port_master[lchip]->network_port[lport] = p_wb_port_prop->network_port;

        cmd = DRV_IOR(DsPhyPortExt_t, DsPhyPortExt_globalSrcPort_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, lport, cmd, &field_val));
        p_usw_port_master[lchip]->port_prop[lport].global_src_port = SYS_MAP_DRV_GPORT_TO_CTC_GPORT(field_val);
        CTC_WB_QUERY_ENTRY_END((&wb_query));
    if (DRV_FROM_AT(lchip))
    {
        /*Get HataRx Format*/
        for(lport = 0; lport < SYS_USW_MAX_PORT_NUM_PER_CHIP; lport++)
        {
            /*Get HataRx Format*/
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_MAC_ID, &mac_id));
            if ((mac_id == DMPS_INVALID_VALUE_U16) || (mac_id == DMPS_INVALID_VALUE_U32))
            {
                continue;
            }
            mac_id = mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_DP);

            /*HataRx/HataTx*/
            step = McHataRxCfg_cfgHataRxTodRtcId1_f - McHataRxCfg_cfgHataRxTodRtcId0_f;
            cmd = DRV_IOR(McHataRxCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, mac_id / MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM), DRV_CMD_PP_EN(cmd), &ds));
            rtc_id = GetMcHataRxCfg(V, cfgHataRxTodRtcId0_f + step*(mac_id % MCHIP_CAP(SYS_CAP_MAC_NUM_PER_QM)), &ds);
            p_usw_port_master[lchip]->port_prop[lport].ptp_domain_id = rtc_id? 1:0;
        }
    }
    /*restore port reflective bmp*/
    for (lport=0; lport<SYS_USW_MAX_PORT_NUM_PER_CHIP; lport++)
    {
        cmd = DRV_IOR(DsDestPort_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &dest_port));
        if (GetDsDestPort(V, reflectiveBridgeEn_f, &dest_port))
        {
            CTC_BMP_SET(p_usw_port_master[lchip]->reflect_en, lport);
        }
    }
done:
   CTC_WB_FREE_BUFFER(wb_query.buffer);

   return ret;
}

/**
 @brief initialize the port module
*/
int32
sys_usw_port_init(uint8 lchip, ctc_port_global_cfg_t* p_port_global_cfg)
{
    int32  ret = CTC_E_NONE;
    uint32 cmd = 0;
    uint32 value = 0;
    uint32 speed_mode = 0;
    uint16 lport = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    sys_usw_port_mac_config_t port_mac_config = {0};
    uint32 port_type = 0;
    uint8  gchip = 0;

    CTC_MAX_VALUE_CHECK(p_port_global_cfg->default_logic_port_en, 1);
    CTC_MAX_VALUE_CHECK(p_port_global_cfg->isolation_group_mode, CTC_ISOLATION_GROUP_MODE_16);
    CTC_MAX_VALUE_CHECK(p_port_global_cfg->use_isolation_id, 1);

    LCHIP_CHECK(lchip);
    if (NULL != p_usw_port_master[lchip])
    {
        return CTC_E_NONE;
    }
    SYS_VCHIP_MASTER_INIT(lchip, p_usw_port_master, CTC_FEATURE_PORT);

    /*alloc&init DB and mutex*/
    p_usw_port_master[lchip] = (sys_port_master_t*)mem_malloc(MEM_PORT_MODULE, sizeof(sys_port_master_t));
    if (NULL == p_usw_port_master[lchip])
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No memory \n");
        return CTC_E_NO_MEMORY;
    }
    sal_memset(p_usw_port_master[lchip], 0, sizeof(sys_port_master_t));
    p_usw_port_master[lchip]->cpu_eth_loop_en = 1;

    CTC_ERROR_GOTO(_sys_usw_port_init_opf(lchip), ret, rollback_0);

    ret = sal_mutex_create(&(p_usw_port_master[lchip]->p_port_mutex));
    if (ret || !(p_usw_port_master[lchip]->p_port_mutex))
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Create mutex fail\n");
        goto rollback_1;
    }

    p_usw_port_master[lchip]->port_prop = (sys_port_prop_t*)mem_malloc(MEM_PORT_MODULE, SYS_USW_MAX_PORT_NUM_PER_CHIP * sizeof(sys_port_prop_t));
    if (NULL == p_usw_port_master[lchip]->port_prop)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No memory \n");
        goto rollback_2;
    }
    sal_memset(p_usw_port_master[lchip]->port_prop, 0, SYS_USW_MAX_PORT_NUM_PER_CHIP * sizeof(sys_port_prop_t));

    p_usw_port_master[lchip]->network_port = (uint16*)mem_malloc(MEM_PORT_MODULE, SYS_USW_MAX_PORT_NUM_PER_CHIP * sizeof(uint16));
    if (NULL == p_usw_port_master[lchip]->network_port)
    {
        SYS_PORT_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No memory \n");
        goto rollback_3;
    }
    sal_memset(p_usw_port_master[lchip]->network_port, 0xFF, sizeof(uint16) * SYS_USW_MAX_PORT_NUM_PER_CHIP);

    /*init asic table*/
    p_usw_port_master[lchip]->use_logic_port_check = (p_port_global_cfg->default_logic_port_en)? TRUE : FALSE;
    if(p_usw_port_master[lchip]->use_logic_port_check)
    {
        value = 0;
        cmd = DRV_IOW(IpeLearningCtl_t, IpeLearningCtl_portSecurityType_f);
        CTC_ERROR_GOTO(DRV_FIELD_IOCTL(lchip, 0, cmd , &value), ret, rollback_4);
    }
    
    if (CTC_WB_STATUS(lchip) != CTC_WB_STATUS_RELOADING)
    {
        CTC_ERROR_GOTO(_sys_usw_port_set_default(lchip, 0, MCHIP_CAP(SYS_CAP_PER_SLICE_PORT_NUM)*MCHIP_CAP(SYS_CAP_LOCAL_SLICE_NUM) - 1), ret, rollback_4);
    }

    /*init isolation mode*/
    _sys_usw_port_isolation_init(lchip, p_port_global_cfg);

    /*init flow ctl*/
    if (MCHIP_PORT(lchip)->port_flow_ctl_init)
    {
        CTC_ERROR_GOTO(MCHIP_PORT(lchip)->port_flow_ctl_init(lchip), ret, rollback_4);
    }

    CTC_ERROR_GOTO(_sys_usw_port_tx_max_frame_size_init(lchip), ret, rollback_4);

    if (CTC_WB_ENABLE(lchip) && CTC_WB_STATUS(lchip) == CTC_WB_STATUS_RELOADING)
    {
        CTC_ERROR_GOTO(sys_usw_port_wb_restore(lchip), ret, rollback_4);
    }
    if (CTC_WB_ENABLE(lchip))
    {
        _sys_usw_port_wb_init(lchip);
    }

    CTC_ERROR_GOTO(SYS_CB_REGISTER(lchip, SYS_CB_QOS_SET_FLOW_CONTROL, sys_usw_port_set_flow_ctl_en), ret, rollback_4);
    CTC_ERROR_GOTO(SYS_CB_REGISTER(lchip, SYS_CB_QOS_GET_FLOW_CONTROL, sys_usw_port_get_flow_ctl_en), ret, rollback_4);

    if(MCHIP_PORT(lchip)->port_init)
    {
        CTC_ERROR_GOTO(MCHIP_PORT(lchip)->port_init(lchip), ret, rollback_4);
    }
    if(DRV_FROM_AT(lchip))
    {
        port_mac_config.is_init = 1;
        CTC_ERROR_GOTO(sys_usw_get_gchip_id(lchip, &gchip), ret, rollback_4);
        for(lport = 0; lport < MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP); lport++)
        {
            dmps_port_info.gport = CTC_MAP_LPORT_TO_GPORT(gchip, lport);
            if ((CTC_E_NONE != sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PORT_TYPE, (void *)&port_type)) || (!SYS_USW_IS_NETWORK_PORT(port_type))
                || (CTC_E_NONE != sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_SPEED_MODE, (void *)&speed_mode)) )
            {
                continue;
            }
            port_mac_config.speed_mode = speed_mode;
            port_mac_config.lport = lport;
            CTC_ERROR_GOTO(sys_usw_port_mac_config_attach(lchip, &port_mac_config), ret, rollback_4);
        }
    }
    p_usw_port_master[lchip]->internal_port_start = MCHIP_CAP(SYS_CAP_INTERNAL_PORT_START);
    return CTC_E_NONE;

rollback_4:
    mem_free(p_usw_port_master[lchip]->network_port);
rollback_3:
    mem_free(p_usw_port_master[lchip]->port_prop);
rollback_2:
    sal_mutex_destroy(p_usw_port_master[lchip]->p_port_mutex);
rollback_1:
    sys_usw_opf_deinit(lchip, p_usw_port_master[lchip]->opf_type_port_sflow);
rollback_0:
    mem_free(p_usw_port_master[lchip]);
    return ret;
}

int32 sys_usw_port_deinit(uint8 lchip)
{
    sys_port_master_t* master_ptr = NULL;
    LCHIP_CHECK(lchip);

    master_ptr = p_usw_port_master[lchip];
    if(NULL == master_ptr)
    {
        return CTC_E_NONE;
    }

    if (SYS_VCHIP_PP_IS_NOT_BASE(lchip))
    {
        p_usw_port_master[lchip] = NULL;
        return CTC_E_NONE;
    }

    sal_mutex_destroy(master_ptr->p_port_mutex);

    if(master_ptr->port_prop)
    {
        mem_free(master_ptr->port_prop);
    }
    if(master_ptr->network_port)
    {
        mem_free(master_ptr->network_port);
    }

    /*opf deinit*/
    sys_usw_opf_deinit(lchip, master_ptr->opf_type_port_sflow);

    mem_free(master_ptr);
    p_usw_port_master[lchip] = NULL;

    return CTC_E_NONE;
}


